Apparatus and method of generating output enable signal for...

Details Apparatus and method of generating output enable signal for... Apparatus and method of generating output enable signal for...

2006-11-16

2008-11-25

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C365S191000

Reexamination Certificate

active

07457191

ABSTRACT:
A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop).clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable signal generator generates an even-numbered output enable signal on the basis of an external read command, the timing signal, a CL (CAS Latency), and the even-numbered divided clock. An odd-numbered output enable signal generator generates an odd-numbered output enable signal on the basis of the external read command, a timing signal in which the timing signal is inverted, the CL, and the odd-numbered divided clock. A logical unit logically operates the even-numbered output enable signal and the odd-numbered output enable signal and outputs an output enable signal.

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