Apparatus and method of error detection and/or correction in a d

Details Apparatus and method of error detection and/or correction in a d Apparatus and method of error detection and/or correction in a d

1980-03-31

1982-10-19

Atkinson, Charles E.

Excavating

371 38, G06F 1110

Patent

active

043553915

ABSTRACT:
Matrix multiplication is used to generate error detection and/or correction binary code bits from a binary input word. A matrix made up of columns and rows of bits set to binary "1"s and "0"s in a pattern conforming to the mathematical expression of a predetermined error detection and/or correction code algorithm is set into a read only memory. The input binary word is 512 bits (64 bytes), one matrix being provided for each of the bytes. The first byte of the 512 bit word is multiplied by its respective matrix providing a ten bit binary code word. Simple odd parity is computed on the first byte and the odd parity bit is appended to the binary code word, which are stored in an accumulator. The next byte is multiplied by its respective matrix to provide another ten bit binary code word, and a simple parity bit is also generated. The second code word and parity bit combination is exclusively ORed in the accumulator with the first binary code word and first parity bit, thereby accumulating the correction and/or detection code. This procedure is continued until all 64 bytes have been handled. The 64 bytes and accompanying eleven error correction and/or detection bits are stored. When recalled from storage, the 64 bytes have the error detection and/or correction bits generated in exactly the same fashion. Means are provided for comparing the new code with the previously computed code. A read-only memory table is provided to locate any erroneous byte to identify the erroneous bit within that byte. Correction circuitry is provided to correct any error within a byte.

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patent: 4201337 (1980-05-01), Lewis et al.
patent: 4214228 (1980-07-01), Nara et al.
patent: 4242752 (1980-12-01), Herkert

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