Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2002-06-25
2004-04-20
Clinger, James (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C345S082000, C345S092000
Reexamination Certificate
active
06724151
ABSTRACT:
This application claims the benefit of Korean Patent Application No. P2001-68871 filed on Nov. 6, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electro luminescence panel, and more particularly to a driving apparatus of an electro luminescence panel that is capable of preventing deterioration of a picture quality caused by the reduction of a driving electric current which occurs when a gate signal is turned off.
2. Discussion of the Related Art
Recently, there have been developed various flat panel display devices reduced in weight and bulk that are capable of eliminating disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) display etc.
Studies for heightening a display quality of the flat panel display device and for providing the flat panel display with a large-scale screen have been actively made. The EL display among these is a self-luminescent device that emits light by itself.
The EL display excites a fluorescent material in use of carriers such as electrons, holes etc to display a picture or video image. It can be driven with a DC voltage and its response speed is fast.
An EL panel, as in
FIG. 1
, includes gate lines GL
1
to GLm and data lines DL
1
to DLn arranged crossing with each other on a glass substrate
10
, and pixel elements PE arranged at each of intersections of the gate lines GL
1
to GLm and the data lines DL
1
to DLn.
Each pixel element PE is driven to generated light corresponding to the size of a pixel signal on the data line DL when gate signals of the gate lines GL
1
to GLm are enabled.
To drive such an EL panel, a gate driver
12
is connected to the gate lines GL
1
to GLm and a data driver
14
is connected to the data lines DL
1
to DLn. The gate driver
12
sequentially drives the gate lines GL
1
to GLm. The data driver
14
supplies the pixel signal to pixel elements PE through the data lines DL
1
to DLn.
In this way, shown in
FIG. 2
, the pixel elements PE driven by the gate driver
12
and the data driver
14
include an electroluminescent (EL) cell, such as an organic light emitting diode OLED, connected to a ground voltage line GND and a cell driving circuit
16
for driving the EL cell OLED.
FIG. 2
is a circuit diagram illustrating the pixel element PE of
FIG. 1
according to a conventional art. It is a driving circuit applied to an intersection of the gate line GL and the data line DL and consists of four thin film transistors (TFTs) T
1
, T
2
, T
3
and T
4
.
Referring to
FIG. 2
, the pixel element PE includes an EL cell OLED connected to a ground voltage source GND and an EL cell driving circuit
16
connected between the EL cell OLED and the data line DL.
The EL cell driving circuit
16
includes first and second PMOS TFT T
1
and T
2
connected to the EL cell OLED and a supply voltage line VDD to form an electric current mirror; a third PMOS TFT T
3
connected to a data line DL and a gate line GL and responding to signals on the gate line GL; a fourth PMOS TFT T
4
connected to a gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
, the gate line GL and the third PMOS TFT T
3
; and the capacitor Cst connected between the gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
, and the supply voltage line VDD.
In operation, if a low input signal, as in
FIG. 3
, is inputted to the gate line GL, the third PMOS TFT T
3
and the fourth PMOS TFT T
4
are turned on. If the third PMOS TFT T
3
and the fourth PMOS TFT T
4
are turned on, the capacitor Cst is charged, via the third PMOS TFT T
3
and the fourth PMOS TFT T
4
, with a video signal of a fixed size that is inputted from the data line DL to synchronize with a scanning signal.
The capacitor Cst is connected with the supply voltage VDD and the gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
, and is charged with the video signal supplied from the data line DL during the low input period of the gate line GL. At this moment, a data voltage, a drain voltage and a pixel voltage in a first node all form the same electric potential, and these voltages are applied to a gate of the second PMOS TFT T
2
. Upon the turn-off of the gate signal, the third PMOS TFT T
3
and the fourth PMOS TFT T
4
are in the state of high impedance, and the capacitor Cst holds the video signal supplied from the data line DL and then charged to it for one frame period.
Due to such a holding period, it is sustained by the capacitor Cst that the video signal supplied from the data line DL is supplied to the EL cell OLED. After it having been held for one frame period, the video signal charged on the capacitor Cst is supplied to the EL cell OLED to display a video image on the display panel.
However, because the input signal is not a perfect rectangular wave upon the turn-off of the gate input signal, the output resistance of the third PMOS TFT T
3
increases while it being turned off. Also, the drain voltage rises in a short time to the supply voltage. When the fourth PMOS TFT T
4
is not turned off in advance, the rise of the drain voltage results in the rise of the pixel voltage. The rise of the pixel voltage drops a gate-source voltage Vgs of the second PMOS TFT T
2
to decrease the brightness of the EL cell OLED. Such a change of the pixel voltage is much bigger than a kick back phenomenon caused by simply capacitive coupling. Even if the time while the gate signal changes from the turn-on state to the turn-off state is reduced or the capacitance is increased, the pixel voltage change does not decrease to a desirable level.
FIG. 5
represents a pixel structure with two gate lines according to a conventional art.
Referring to
FIG. 5
, a pixel element PE includes an EL cell OLED connected to a ground potential source GND, and an EL cell driving circuit
26
connected between the EL cell OLED and a data line DL.
The EL cell driving circuit
26
includes first and a second PMOS TFT T
1
and T
2
connected to the EL cell OLED and a supply voltage line VDD to form an electric current mirror; a third PMOS TFT T
3
connected to a data line DL and a first gate line GL
1
and responded to signals on the gate line GL; a fourth PMOS TFT T
4
connected to a gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
, a second gate line GL
2
and the third PMOS TFT T
3
; and a capacitor Cst connected between the gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
, and the supply voltage line VDD.
In operation, if a low input signal, as in
FIG. 6
, is inputted to the first and second gate lines GL
1
and GL
2
at the same time, the third PMOS TFT T
3
and the fourth PMOS TFT T
4
are turned on. If the third PMOS TFT T
3
and the fourth PMOS TFT T
4
are turned on, the capacitor Cst is charged via the third PMOS TFT T
3
and the fourth PMOS TFT T
4
with a video signal of a fixed size that is inputted from the data line DL to synchronize with a scanning signal. In other words, the capacitor Cst is connected with the supply voltage VDD and the gate electrode of the first PMOS TFT T
1
and the second PMOS TFT T
2
and is charged with the video signal supplied from the data line DL during the low input period of the first and second gate lines GL
1
and GL
2
.
After this, by inputting a high input signal to the second gate line GL
2
before the first gate line GL
1
, the fourth PMOS TFT T
4
is made to be in a high impedance state beforehand as in
FIG. 7A
to have the pixel voltage sustain the data voltage. (Vdata=Vdrain=Vpixel) Then, even if the first gate line GL
1
is turned off by inputting the high input signal to the first gate line GL
1
, and even if the drain voltage Vdrain rises to the supply voltage as in
FIG. 7B
, it does not have an effect on the pixel voltage Vpixel.
However, because two gate lines GL
1
and GL
2
shou
Alemu Ephrem
Clinger James
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
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