Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1999-07-15
2000-12-05
Tung, Kee M.
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
345506, G06F 1580
Patent
active
061573930
ABSTRACT:
An apparatus for and method of directing graphical data toward a display device from a plurality of graphics processors couples the graphics processors in a manner that reduces the size of the interface on each graphics processor. In particular, each graphics processor produces graphical data for an associated set of pixels on the display device, where each pixel is represented by a first amount of graphical data. The graphics processors are arranged so that one of the graphics processors is a destination processor. The total number of graphics processors that are not designated as the destination processor thus constitute a remaining number. Each graphics processor produces a second amount of graphical data during each clock cycle of a common clock. The first amount of graphical data, however, is comprised of at least substantially two times the second amount of graphical data. The graphics processors then are coupled so that during each clock cycle, the destination processor receives no more graphical data from the other processors than an amount equal to the product of the remaining number and the second amount.
REFERENCES:
patent: 4434437 (1984-02-01), Strolle et al.
patent: 4615013 (1986-09-01), Yan et al.
patent: 4646232 (1987-02-01), Chang et al.
patent: 4908780 (1990-03-01), Priem et al.
patent: 4918626 (1990-04-01), Watkins et al.
patent: 4991122 (1991-02-01), Sanders
patent: 5107415 (1992-04-01), Sato et al.
patent: 5123085 (1992-06-01), Wells et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5287438 (1994-02-01), Kelleher
patent: 5293480 (1994-03-01), Miller et al.
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5363475 (1994-11-01), Baker et al.
patent: 5371840 (1994-12-01), Fischer et al.
patent: 5394524 (1995-02-01), DiNicola et al.
patent: 5398328 (1995-03-01), Weber et al.
patent: 5446479 (1995-08-01), Thompson et al.
patent: 5485559 (1996-01-01), Sakaibara et al.
patent: 5511165 (1996-04-01), Brady et al.
patent: 5519823 (1996-05-01), Barkans
patent: 5544294 (1996-08-01), Cho et al.
patent: 5555359 (1996-09-01), Choi et al.
patent: 5557734 (1996-09-01), Wilson
patent: 5561749 (1996-10-01), Schroeder
patent: 5572713 (1996-11-01), Weber et al.
patent: 5631693 (1997-05-01), Wunderlich et al.
patent: 5664114 (1997-09-01), Krech, jr. et al.
patent: 5666520 (1997-09-01), Fujita et al.
patent: 5684939 (1997-11-01), Foran et al.
patent: 5701365 (1997-12-01), Harrington et al.
patent: 5706481 (1998-01-01), Hannah et al.
patent: 5721812 (1998-02-01), Mochizuki
patent: 5737455 (1998-04-01), Harrington et al.
patent: 5757375 (1998-05-01), Kawase
patent: 5757385 (1998-05-01), Narayanaswami et al.
patent: 5764237 (1998-06-01), Kaneko
patent: 5821950 (1998-10-01), Rentschler et al.
patent: 5841444 (1998-11-01), Mun et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5883641 (1999-03-01), Krech, Jr. et al.
patent: 5914711 (1999-06-01), Mangerson et al.
patent: 6008821 (1999-12-01), Bright et al.
"A Fine Grained Data Flow Machine and Its Concurrent Execution Mechanism," Iwashita et al., C&C Information Technology Research Labs, Apr. 1989, pp. 63-72.
"A Dataflow Image Processing System TIP-4, " Fujita et al., C&C Information Technology Research Labs, NEC Corporation, Sep. 1989, pp. 735-741.
"Processing the New World of Interactive Media," Rathnam, The Trimedia VLIW CPU Architecture, Mar. 1998, pp. 108-117.
"Effective Cache Mechanism for Texture Mapping," IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996, pp. 213-217.
"Advanced Raster Graphics Architecture," XP-002118066, pp. 890-893.
"Data-Format Conversion: Intel/Non-Intel," vol. 33, No. 1A, Jun. 1990, IBM Technical Disclosure Bulletin, pp. 420-427.
"Address Munging Support in a Memory Controller/PCI Host Bridge for the PowerPC 603 CPU Operating in 32-Bit Data Mode," IBM Technical Disclosure Bulletin, vol. 38, No. 09, Sep. 1995, pp. 237-240.
"One Frame Ahead: Frame Buffer Management for Animation and Real-Time Graphics," XP-000749898, Auel et al., Tektronix Inc., pp. 43-50.
"Efficient Alias-Free Rendering Using Bit-Masks and Look-Up Tables," Abram et al., The University of North Carolina at Chapel Hill, XP-002115680, Jul. 1985, pp. 53-59.
"A New Simple and Efficient Antialiasing with Subpixel Masks," Schilling et al., Computer Graphics, vol. 25, No. 4, Jul. 1991, pp. 133-141.
"A Multiprocessor System Utilizing Enhanced DSP's for Image Progressing," Ueda et al., XP 2028756, pp. 611-619.
"The Reyes Image Rendering Architecture," Cook et al., Computer Graphics, vol. 21, No. 4, Jul. 1987, pp. 95-102.
"The Accumulation Buffer: Hardware Support for High-Quality Rendering," Haeberli et al., Computer Graphics, vol. 24, No. 4, Aug. 1990, pp. 309-318.
"Advanced Animation and Rendering Techniques," Watt et al., ACM Press, New York, New York, pp. 127-137.
The A-Buffer, an Antialiased Hidden Surface Method, Carpenter, Loren, Computer Graphics, vol. 18, No. 3, Jul. 1984, pp. 13-18.
Potter Michael
Whitmore Clifford A.
Intergraph Corporation
Tung Kee M.
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