Apparatus and method of controlling bank of semiconductor...

Details Apparatus and method of controlling bank of semiconductor... Apparatus and method of controlling bank of semiconductor...

2006-10-27

2008-11-18

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S191000

Reexamination Certificate

active

07453757

ABSTRACT:
An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.

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patent: 6694422 (2004-02-01), Kim
patent: 2005/0140969 (2005-06-01), Kang et al.
patent: 2005/0141255 (2005-06-01), Ko et al.
patent: 215663 (2000-08-01), None
patent: 1020050041621 (2005-05-01), None

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