Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
1999-05-24
2002-08-27
Chin, Wellington (Department: 2664)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S468000, C370S229000, C370S429000, C710S310000, C710S311000
Reexamination Certificate
active
06442137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to networks and more particularly, to a system and method of controlling network traffic data in a full-duplex switched network operating according to Ethernet (IEEE 802.3) protocol.
BACKGROUND ART
Switched local area networks use a network switch for supplying data frames between network stations or other network nodes, where each network node is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) enabling a network interface within each network node and the network switch to access the media. The network switch stores and forwards data frames received from a transmitter node to a destination node based on header information and the data in the received frames, including source and destination address. An external memory, such as an SSRAM, is used by the network switch to temporarily store the data frames as they are passed through the switch. In particular, the network switch stores and fetches data frames in the external memory via an external memory bus.
A difficulty in designing a network switch to be “non-blocking” (i.e., preventing delay in transferring a data packet received at an input switch), yet with limited memory bandwidth resources, is ensuring that each port of the network switch has sufficient memory resources allocated from the external memory to prevent the delay of data transmission. The external memory bus of an SSRAM, for example, has a limited bandwidth based on the number of data bits on the external memory bus (e.g., 16-bit, 32-bit, etc.) and the data rate of the bus. Hence, a network switch may allocate a fixed number of time slots for each port of the network switch. However, the data traffic on higher speed switch ports may exceed the bandwidth capacity of the external memory bus.
Previous switches have been proposed which assign memory slots to ports using a request based arbitration scheme that grants memory slots to ports requesting slots on a “first come, first serve” basis. As the slots are requested, an arbitrator grants slots in answer to the requests as they are received, but only after previously requested slots have been completed. The request based arbitration; scheme, however, is complex and difficult to implement, increasing the likelihood for errors. From an implementation standpoint, such arbitration schemes present more difficulty in controlling the memory allocation.
Other systems have included fixed slot schemes which assign a fixed amount of bandwidth to each slot of the network switch. However, these systems are expensive since sufficient bandwidth capacity must be provided to all of the slots at all times. Also, since ports are not fully utilized at all times, much of the assigned bandwidth is wasted due to times of inactivity on a network switch port.
SUMMARY OF THE INVENTION
There is a need for allocating limited memory bandwidth among network switch ports based on detected network traffic conditions on the network switch ports. In particular, there is a need for selectively reassigning memory slots between high data rate ports of a network switch to optimize use of limited bandwidth resources in a non-blocking switch.
There is also a need to minimize the use of complex arbitration schemes by controlling memory slot allocation using easier to implement arrangements.
These and other needs are attained by the present invention, where the limited memory bandwidth slots are selectively reassigned between high data rate ports dependent upon which ports are encountering higher network traffic to achieve efficient and inexpensive allocation of the memory bandwidth resources.
According to one aspect of the invention, a network switch includes a first port having an initially assigned first number of memory access slots and a second port having an initially assigned second number of memory access slots less than the first number of memory access slots. In addition, the network switch includes an external memory interface configured for transferring packet data at a prescribed data rate between the network switch and an external memory. The external memory interface includes a scheduler that assigns the initially allocated first and second numbers of memory access slots of the first and second ports, respectively. Furthermore, the scheduler selectively reassigns the first number of memory access slots to the second port and the second number of memory access slots to the first port based on the first port encountering less network traffic relative to the second port. The feature of the scheduler selectively reassigning or, in other words, selectively “swapping” the memory access slots assigned to the high data rate ports, allows the present invention to efficiently allocate limited memory bandwidth resources while achieving an inexpensive and easily implemented network switch.
Additionally, the second port includes a clock mutliplexer configured for selectively changing a data rate (i.e., the rate at which the port transmits and receives data externally over a media) of the second port based on the number of assigned memory slots assigned to the first and second ports. This feature prevents overflow and underflow conditions in the second port which may occur as the allocated bandwidth of the second port varies according to the reassignment of memory access slots.
According to another aspect of the invention, a method assigns memory access slots between first and second ports of a network switch having an external memory interface configured for transferring packet data to an external memory, the external memory interface including a scheduler for assigning memory access slots. The method includes assigning an initial first and second number of memory access slots to the first and second ports, respectively, the second number of memory access slots being less than the first number of memory access slots. Next, the scheduler determines whether the first port is encountering less network traffic relative to the second port. The first number of memory access slots are selectively reassigned to the second port and the second number of memory access slots are selectively reassigned to the first port based on a determination that the first port encountering less network traffic relative to the second port. The selective reassignment of memory access slots by swapping the assignments eliminates the need for complex arbitration schemes and, hence, allows the present invention to inexpensively and easily implement efficient allocation of limited memory bandwidth resources.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4181933 (1980-01-01), Benysek
patent: 5515376 (1996-05-01), Murthy et al.
patent: 6052738 (2000-04-01), Muller et al.
patent: 6052751 (2000-04-01), Runaldue et al.
Chiang John M.
Egbert Chandan
Erimli Bahadir
Lam Ian
Leung Eric Tsin-Ho
Advanced Micro Devices , Inc.
Chin Wellington
Schultz William
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