Multiplex communications – Data flow congestion prevention or control – Flow control of data transmission through a network
Reexamination Certificate
1999-05-24
2002-12-31
Chin, Wellington (Department: 2664)
Multiplex communications
Data flow congestion prevention or control
Flow control of data transmission through a network
C370S230000, C370S235000, C370S237000
Reexamination Certificate
active
06501734
ABSTRACT:
TECHNICAL FIELD
The present invention relates to networks and more particularly, to a system and method of controlling network traffic data in a full-duplex switched network operating according to Ethernet (IEEE 802.3) protocol.
BACKGROUND ART
Switched local area networks use a network switch for supplying data frames between network stations or other network nodes, where each network node is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) enabling a network interface within each network node and the network switch to access the media. The network switch stores and forwards data frames received from a transmitter node to a destination node based on header information and the data in the received frames, including source and destination address. An external memory, such as an SSRAM, is used by the network switch to temporarily store the data frames as they are passed through the switch. In particular, the network switch stores and fetches data frames in the external memory via an external memory bus.
A difficulty in designing a network switch to be “non-blocking” (i.e., preventing delay in transferring a data packet received at an input switch port) yet with limited memory bandwidth resources, is to ensure that each port of the network switch has sufficient memory resources allocated from the external memory to prevent the delay of data transmission. The external memory bus of an SSRAM, for example, has a limited bandwidth based on the number of data bits on the external memory bus (e.g., 16-bit, 32-bit, etc.) and the data rate of the bus. Hence, a network switch may allocate a fixed number of time slots for each port of the network switch. However, the data traffic on higher speed switch ports may exceed the bandwidth capacity of the external memory bus.
Previous switches have been proposed which assign memory slots to ports using a request based arbitration scheme that grants memory slots to those ports requesting slots on a “first come, first serve” basis. As the slots are requested, an arbitrator grants slots in answer to the requests as they are received, but only after previously requested slots have been completed. The flexible arbitration scheme, however, is complex and difficult to implement, increasing the likelihood for errors. From an implementation standpoint, such arbitration schemes present more difficulty in controlling the memory allocation.
Other systems have included fixed slot schemes which assign a fixed amount of bandwidth to each slot of the network switch. However, these systems are expensive since sufficient bandwidth capacity must be provided to all of the slots all of the time. Also, since ports are not always fully utilized at all times, much of the assigned bandwidth is wasted due to times of inactivity on a network switch port.
DISCLOSURE OF THE INVENTION
There is a need to efficiently allocate limited memory bandwidth resources by dynamically assigning memory slots between ports of a network switch to avoid wasting of bandwidth resources and more costly systems.
There is also a need to minimize the use of complex arbitration schemes by controlling memory allocation using arrangements that are easier to implement.
These and other needs are attained by the present invention, where lower bandwidth ports are assigned fixed bandwidth slots and higher bandwidth ports are dynamically allocated reserved bandwidth slots based on a detected presence of slot requests received from one of the higher bandwidth ports.
According to one aspect of the invention, a network switch includes one or more first ports configured for transferring packet data at a first data rate, at least one second port configured for transferring packet data at a second data rate higher than the first data rate and at least one third port configured for transferring packet data at a third data rate higher than the first data rate. The network switch also includes an external memory interface configured for transferring packet data between the switch and an external memory according to a prescribed bandwidth. The external memory interface includes a scheduler that assigns slots for data transfer according to the prescribed bandwidth. The scheduler assigns a first group of slots as fixed slots for the first ports, respectively. In addition, the scheduler dynamically assigns a second selected group of slots between the second port and the third port based on a detected presence of a slot request received from one of the second or third ports.
According to another aspect of the invention, a method in a network switch assigns bandwidth slots between ports of a network switch configured for transferring packet data to an external memory at a prescribed bandwidth. The method includes first assigning a predetermined number of bandwidth slots to a respective number of network switch ports and reserving a remaining number of the bandwidth slots for higher rate switch ports. Next, the method determines whether one higher rate port has generated a bandwidth request to an external memory interface for one of the reserved remaining bandwidth slots within a prescribed period of time. If a bandwidth request is generated, the reserved bandwidth slot is assigned to the requesting higher rate port in response to detection of the bandwidth request to the external memory interface within the prescribed period of time. If an absence of the bandwidth request is determined within the prescribed period of time, the one reserved bandwidth slot is assigned to a second higher rate port. The first assigning of the predetermined number of slots eliminates the need for a request based arbitration scheme and reduces the amount of logic needed to determine allocation of the remaining slots to the higher rate switch ports. The selective assignment of slots between two higher rate data ports based on whether or not a slot request is issued eliminates the necessity for complex logic, such as a flexible arbitration scheme, to determine the slot allocation. Hence, implementation is less costly while efficiently utilizing limited memory bandwidth resources.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4181933 (1980-01-01), Benysek
patent: 5515376 (1996-05-01), Murthy et al.
patent: 6052738 (2000-04-01), Muller et al.
patent: 6052751 (2000-04-01), Runaldue et al.
Chiang John M.
Egbert Chandan
Erimli Bahadir
Lam Ian
Leung Eric Tsin-Ho
Advanced Micro Devices , Inc.
Chin Wellington
Schultz William
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