Apparatus and method identifying false timing paths in digital c

Details Apparatus and method identifying false timing paths in digital c Apparatus and method identifying false timing paths in digital c

1996-07-12

1997-10-07

Beausoliel, Jr., Robert W.

Excavating

39518309, 371 27, 364578, G01R 3128

Patent

active

056757280

ABSTRACT:
A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a "1" at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a "1" within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.

REFERENCES:
patent: 4556840 (1985-12-01), Russell
patent: 4852093 (1989-07-01), Koeppe
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5023485 (1991-06-01), Sweeney
patent: 5095454 (1992-03-01), Huang
patent: 5138579 (1992-08-01), Tatsumi et al.
patent: 5191541 (1993-03-01), Landman et al.
patent: 5200907 (1993-04-01), Tran
patent: 5319646 (1994-06-01), Simpson et al.
patent: 5377197 (1994-12-01), Patel et al.
patent: 5387825 (1995-02-01), Cantrell et al.
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5452239 (1995-09-01), Dai et al.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, Nov. 8-12, 1992, no. Conf. 10, Institute of Electrical and electronics engineers, pp. 258-262.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, Nov. 8-12, 1992, no. Conf. 10, 8 Nov. 1992, Institute of Electrical Electronics Engineers, p. 510-517.
Proceedings of the ACM/IEEE Design Automation Conference, San Francisco, Jun. 17-21, 1991, no. Conf. 28, 17 Jun. 1991 Institute of Electrical and Electronics Engineers, pp. 551-554.

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