Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1998-07-17
2001-03-20
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S519000
Reexamination Certificate
active
06204864
ABSTRACT:
BACKGROUND OF THE INVENTION
The subject matter of the present application is related to subject matter disclosed in U.S. patent application Ser. No. 08/486,796, which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,694,141 for a Computer System with Double Simultaneous Displays Showing Differing Display Images; in U.S. patent application Ser. No. 08/485,876, which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,673,416 for a Display FIFO Module including a Mechanism for Issuing and Removing Requests for DRAM Access; in U.S. patent application Ser. No. 08/487,120 which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,724,063 for a Computer System with Dual-Panel LCD Color Display; and in U.S. patent application Ser. No. 08/487,121, which was abandoned in favor of U.S. patent application Ser. No. 08/872,244, which was filed on Jun. 10, 1997, for a Computer System with Video Display Controller having Power Saving Modes now U.S. Pat. No. 5,886,689.
1.Field of the Invention
The present invention relates generally to a computer system with one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for example. The display devices provide a user of the computer system with a visible display of computer data, such as text or graphics. More particularly, the present invention is in the field of a computer system having a graphics generator, and a video display controller (VDC) for such a computer system. Via a bus interface, the VDC receives image information, such as text or graphics generated by a processor (CPU) or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and provides signals driving one or both of the CRT or LCD displays.
Still more particularly, the present invention is in the field of a VDC having a sequencer and controller (SEQC) for a dynamic random access memory (DRAM) of the VDC. Image information to be displayed on the CRT or LCD is stored in the DRAM in preparation to being transferred to a video memory of the first-in-first-out (FIFO) type. In addition to the FIFO and CPU, other devices of the computer system, such as a bit block transfer engine (bit-BLT) (i.e., a graphics generator) a request access to the DRAM. The SEQC arbitrates requests for access to the DRAM by the various devices of the computer system and prioritizes these requests for access to insure both that the display FIFO is not denied data for display and that most-efficient access to the DRAM is provided to the other devices of the computer system.
2.Related Technology
A conventional bus arbitrating circuit is known in accord with U.S. Pat. No. 4,453,214 (hereinafter, the '214 patent), issued Jun. 5, 1984 to Ralph L. Adcock. According to the '214 patent, a bus arbitrator and memory manager (BAMM) establishes a priority among competing operating units of a computer system. The BAMM sorts requests for access to the memory according to a priority, and allows the device with the highest priority access ahead of the other devices. It appears that once a device is allowed access to the memory, an interrupt of this access is not allowed when a request for access from another device with a higher priority is received by the BAMM of the '214 patent. When a device which has had memory access is finished with this access, it provides a “sign off” signal, thus allowing the BAMM to permit memory access to the device requesting access and having the highest priority.
With a BAMM of the type disclosed by the '214 patent, a display FIFO of a computer system could conceivably be denied access to the DRAM at a time when a display FIFO is nearly or completely out of information for display. Thus, continuity of operation of the display of the computer system could be interrupted. Understandably, this type of display interrupt would be concerning and confusing for a user of the computer system.
Another conventional graphics system with a graphics controller and DRAM controller is known in accord with U.S. Pat. No. 4,991,112 (hereinafter, the '112 patent), issued Feb. 5, 1991 to Jean-Michel Callemyn. According to the '112 patent, a DRAM controller receives refresh requests and requests for access to the DRAM in bursts, and arbitrates among the requests. During a display stage, after a preparatory read, the greatest priority is given to the display FIFO. A read of the DRAM in bursts may be interrupted when the FIFO is full. In this case, priority is given to a possible preparatory read. In the absence of a preparatory read request, a request by the CPU will be honored and access to the DRAM will be effected for the CPU. As soon as the FIFO makes a request for access, however, the CPU access will be interrupted, and the previously interrupted read in bursts for the FIFO with be resumed. During the line return stage, differing priorities are set for access to the DRAM. That is, refreshing the DRAM is given highest priority, followed by filling of the display FIFO. Third in priority is compliance with access requests from the graphics processor, and then accesses for the CPU. However, other than the interrupt described above, the '112 patent is not believed to allow interruption of an access to the DRAM once this access is allowed. Additionally, the interrupt allowed by the '112 patent is an inherent interrupt necessary to prevent data of the FIFO from being overwritten by new data because the FIFO is full.
Yet another conventional DRAM refresh controller with a bus arbitration scheme is known in accord with U.S. Pat. No. 5,345,577 (hereinafter, the '577 patent), issued Sep. 6, 1994, to Tzoyao Chan and Milton Cheung. According to the '577 patent, a cache controller is provided with both burst and hidden refresh modes. Refresh requests are counted but not acted upon by allowing memory access until a certain number of these requests are received. On the other hand, hidden refreshes are done with no hold signal being sent to the CPU while the refresh is done. Until the refresh is completed local memory access but not remote memory access is allowed. Consequently, the CPU is denied memory access during a hidden refresh, but will not expect immediate access to the memory anyway so that the hidden refresh does not interfere with CPU operation. Interruption of memory access once granted does not appear to be a feature of this patent.
Taking general considerations into account, in a graphics controller, such as a VDC generally described above, arbitrating DRAM interface (access) among the several devices of the system is the most critical portion of the controller. Access to the DRAM dictates how and when devices such as the bit-BLT engine, display FIFO, and the local bus (that is, the CPU) have access to the DRAM. Access requests by the CPU and bit-BLT engine are mutually exclusive, and will not occur simultaneously. Ordinarily, whenever access to the DRAM is discontinued for one device and allowed for another device, a new page of the DRAM must be accessed. That is, the DRAM may be visualized as a two-dimensional array of memory locations. This memory uses rows and columns of memory locations (or memory cells) with a row pointer and a column pointer. As long as memory access is made to a single row of the memory, with the column pointer simply moving along the row as data is written to or read from address locations of the row, then a single-page access to the memory is effected, and no page break is necessary. However, when another row (i.e., another page) of the memory must be accessed, a pre-charge sequence must be run in preparation to accessing the next row of memory locations. This pre-charge sequence takes time so that a multiple-page access to the memory is not nearly as efficient as a single-page access in terms of the amount of data written into or read from the memory during the time interval of such a memory access.
Thus, page-mode access to the DRAM is much more efficient in terms of time utilization than is random access to the DRAM because of th
Seiko Epson Corporation
Tung Kee M.
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