Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
2000-08-25
2004-10-12
Christensen, Andrew (Department: 2615)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S283000
Reexamination Certificate
active
06803951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video image information processing apparatus preferable for being equipped on, for example, digital video camera and the like, and more particularly to a video image information processing apparatus and video image information processing method wherein by providing with a memory means for memorizing video image information sent from an image pickup means such as solid-state image sensing device (e.g. Charge Coupled Device (CCD)) or the like temporarily and controlling a write timing for writing the video image information to this memory means, it is intended to cancel a delay in information processing generated between the image pickup means and the information processing means.
2. Description of the Related Art
Conventionally, a digital video camera which handles video signals generated by taking pictures of an object using, for example, the solid-state image sensing device (e.g. Charge Coupled Device (CCD)) in digital manner has been well known. A schematic construction of this digital video camera is as shown in FIG.
1
. More specifically, an image pickup beam corresponding to an object impinges upon a CCD
102
through an optical lens
101
.
The CCD photoelectrically converts the impinging image pickup beam to form signal charge and accumulates this. This signal charge is read out according to output timing signal supplied from a timing generator
110
and supplied to a CDS.AGC circuit
103
as an image pickup signal.
The CDS.AGC circuit
103
carries out correlated double sampling (CDS) processing and automatic gain control (AGC) processing on the image pickup signal from the CCD
102
and supplies this to the A/D converter
104
(analog/digital). The A/D converter
104
digitizes this image pickup signal to form image pickup data and supplies this to a signal processing circuit
105
composed of for example, digital signal processor (DSP) and the like.
Here, so-called frame transfer type in which the CCD reads out two lines at the same time and outputs an image pickup signal of a frame in a period of {fraction (1/60)} sec has been well known. If a description is progressed assuming that this frame transfer type CCD is provided as the aforementioned CCD, it comes that the aforementioned image pickup data of two lines are supplied from the CCD
102
to the signal processing circuit
105
at the same time.
The signal processing circuit
105
comprises a Y/C separating circuit
121
(luminance/color separating circuit), a field memory controller
122
(FMC) having a field memory for storing luminance data Y and color data C, and the like. The image pickup data of two lines inputted at the same time is separated to luminance data Y and color data C subjected to signal processing by the Y/C separating circuit
121
and the two lines are supplied to the FMC
122
at the same time.
The FMC
122
controls write and read of the luminance data Y and color data C into the field memory based on a line address signal supplied from the address controller
111
under a control of the control circuit
112
(CPU). The luminance data Y and color data C read out from the respective field memories of the FMC
122
are supplied to data processing system of subsequent stage (not shown) such as a recording block and external output block through an output terminal
106
and an output terminal
107
.
In the digital video camera unit shown in
FIG. 1
, read-out control of the CCD
102
by means of a timing generator
110
, Y/C separating processing in the Y/C separating circuit
121
of the signal processing circuit
105
, memory control in the FMC
122
and the like are carried out with HD signal (horizontal synchronous signal) and VD signal (vertical synchronous signal) generated by the SSG (synchronous signal generating portion)
123
in the signal processing circuit
105
.
Here, an operating timing of each portion of the conventional digital video camera unit shown in
FIG. 1
will be described taking an example of processing in the horizontal direction as an example.
In the horizontal direction processing, at which clock from a rise of the HD signal an image pickup signal is read out from the CCD
102
, how many clocks of delay occur when that image pickup signal is subjected to Y/C separating processing and how many clocks of delay occur when a signal is inputted to the field memory control portion
122
are evident on a design stage.
Thus, a reference signal for processing based on the HD signal and VD signal, that is, a reference count acting as a criterion for the Y/C separating processing, memory control processing in the FMC
122
and the like can be set up base on clock delay information known at the time of design. Therefore, if the reference count acting as criterion for the Y/C separating processing, remote control processing in the FMC
122
and the like is set up by means of a microcomputer or the like, the digital video camera unit is capable of carrying out the Y/C separating processing, memory control processing and the like in which the clock delay is compensated.
However, on the other hand, a signal delay amount (analog delay amount) in an analog path from the CCD
102
to an input stage of an A/D converter
104
through the CDS.AGC circuit
103
is not evident on the design stage. That is, the analog delay amount mentioned here means a delay amount generated by analog devices (analog devices constituting mainly CDS.AGC circuit
103
) on the analog path. Because the characteristics of the respective analog devices composing the analog path deviate minutely, it is difficult to control the analog delay amount preliminarily at the time of design.
Thus, the analog delay amount has to be measured (recognized) using an individual digital video camera unit (actual machine) produced actually.
Further, after the analog delay amount is measured using the actual machine as described above, it is necessary to set up the aforementioned reference count set up by the microcomputer again in order to absorb the measured analog delay amount. This fact complicates production process and adjustment process of the digital video camera units, which is an obstacle against a demand for reducing production cost.
Generally, in various products, the specifications of individual parts used in the products are often changed even after its design is completed and the same thing happens in the digital video camera unit. For example, if in the digital video camera unit shown in
FIG. 1
, the reading method of the CCD
102
is changed due to technical progress or change of use purpose, the signal processing circuit
105
which coincides with the design specification originally sometimes becomes incapable of coinciding with the changed reading method. More specifically, in case where the CCD
102
which reads out two lines at the same time is changed to a CCD type which reads out a single line, the signal processing circuit
105
of the type for reading out two lines at the same time is not capable of corresponding to such a change.
Thus, if it is intended to change the CCD reading method from the two-line simultaneous reading method to the single line reading method, the signal processing circuit has to be changed corresponding to that reading method change. Thus, because the structure of the signal processing circuit has to be changed largely, there is a fear that production cost may increase due to procurement of new components, change in production process and the like. Although it can be considered to provide with a signal processing circuit capable of corresponding to various reading methods of the CCD, the signal processing circuit of this case becomes a very special one, so that necessarily the price increases, which is not favorable.
Further, if the driving frequency of the CCD
102
is changed, the operating frequency of the signal processing circuit
105
has to be changed correspondingly. In this case, not only the signal processing circuit
105
but also the entire design has to be reviewed so that a large
Kuhara Takehiko
Matsukawa Nobuyuki
Berkowitz Marvin C.
Christensen Andrew
Nath & Associates PLLC
Victor Company of Japan , Limited
Wu Dorothy
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