Apparatus and method for updating a status register in an...

Details Apparatus and method for updating a status register in an... Apparatus and method for updating a status register in an...

2007-07-10

2007-07-10

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S222000, C712S225000

Reexamination Certificate

active

10423211

ABSTRACT:
An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that indicates that an instruction is the most recently issued instruction. The dispatch unit resets the MRI bit flag for all other instructions. Each execution stage of the execution pipeline keeps track of the MRI bit flag information for the instruction. A writeback unit updates the status register after the execution of the instruction that has its MRI bit flag set. The writeback unit does not update the status register for instructions that have their MRI bit flag reset. This allows the instruction to be identified that is the most recent instruction to enter the dispatch unit.

REFERENCES:
patent: 5826070 (1998-10-01), Olson et al.
patent: 6151669 (2000-11-01), Huck et al.
patent: 2002/0078287 (2002-06-01), Shinagawa et al.
Microsoft Computer Dictionary, 2002, Microsoft Press, 5th edition.

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