Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Patent
1994-11-02
1997-07-22
Chin, Stephen
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
375265, 371 43, H04L 100
Patent
active
056510322
ABSTRACT:
A digital data processing apparatus capable of reducing a circuit scale without deteriorating error-correcting capability, and capable of reducing the bit number of a branch metric calculating circuit. The apparatus includes: a region determining portion which determines an optimal bit number corresponding to the number of representative symbol groups; a delaying portion which delays an output from the region determining portion for as long as a coded bit is decoded by a Viterbi decoding portion; and a decoding portion which inputs and decodes an output from the delaying portion and a coded bit that is decoded by the Viterbi decoding portion so as to be decoded, and which outputs the uncoded bit.
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G. Feygin et al., "A Multiprocessor Architecture for Viterbi Decoders with Linear Speedup", IEEE Transactions on Signal Processing 41(9): 2907-2917 (1993).
Ungerboeck, "Trellis-Coded Modulation With Redundant Signal Sets Part I: Introduction", IEEE Communications Magazine, vol. 25, No. 2, pp. 5-11, (1987).
Viterbi et al., "A Pragmatic Approach To Trellis-Coded Modulation", IEEE Communications Magazine, pp. 11-19, (1989).
Pottie et al., "Multilevel Codes Based on Partitioning", IEEE Transactions On Information Theory, vol. 35, No. 1, pp. 87-98, (1989).
Chin Stephen
Kabushiki Kaisha Toshiba
Kim Kevin
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