Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-05-18
2003-09-02
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S094000
Reexamination Certificate
active
06614424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for transmission of parallel data, and more specifically, a method and apparatus for data transmitting apparatus for minimizing the electromagnetic interference (EMI) that is generated during parallel data transmission. Further, the present invention also relates to a liquid crystal display (LCD) device including such a data transmitting apparatus and method.
2. Description of the Related Art
Presently, the video data that is transmitted through a transmission medium includes enlarged content in order to meet the requirements for higher quality images. Further, the data is transmitted at very high speed so that the data can be used at the desired times by a user. Accordingly, the transmission frequency of the video data has been increased and the number of transmission lines to transmit the information has also been increased. However, when video data is transmitted at high frequencies synchronously and simultaneously over the increased data transmission lines, serious problems related to EMI result.
Referring to
FIG. 1
, there is shown an LCD driving apparatus for transmitting a video data into a direct driving system. The LCD driving apparatus includes source drive integrated circuits (ICs)
12
to drive the source lines of an LCD (not shown). The LCD driving apparatus also includes an LCD controller
10
to control the driving times of the source drive ICs
12
. The LCD controller
10
responds to a clock signal MCLK and horizontal and vertical synchronizing signals Hsync and Vsync that are inputted externally to control the driving times of the gate drive ICs (not shown) and the source drive ICs
12
. In other words, the LCD controller
10
responds to the input clock signal MCLK and the horizontal and vertical synchronizing signals Hsync and Vsync to output a gate clock signal GCLK and a gate control signal GCS to control the operation of the gate drive ICs.
Referring to
FIG. 2
, the LCD controller
10
of
FIG. 1
responds to an input clock signal MCLK and the horizontal and vertical synchronizing signals Hsync and Vsync to output the red, green and blue data designated as RD, GD and BD that is input into an enable region of a DTMG signal to inform the video data region of the source drive ICs
12
. In the above-described case, the LCD controller
10
is synchronized to a source clock signal SCLK which has the same frequency as the input clock signal MCLK along with a source control signal SCS to control the operation of the source drive ICs
12
by transmitting the data RD, GD and BD to the source drive ICs
12
.
The source drive ICs
12
sample the RD, GD and BD data that is input by the LCD controller in accordance with the source clock signal SCLK. Since each of the data RD, GD and BD consists of a 6 bit signal, a data bus that is connected to the LCD controller
10
consists of 18 data lines. However, as data RD, GD and BD are synchronously supplied over the 18 data lines, an EMI problem occurs at the data bus. More specifically, as the resolution of the LCD is increased, which means as the number of pixels,is increased, the amount of video data that needs to be transmitted within a unit of time also needs to be increased. For example, when the LCD is in XGA mode, the LCD controller
10
drives all of the input and output clock signals MCLK and SCLK at 65 MHz, thus the source drive ICs
12
inputs or outputs the data RD, GD and BD with the output clock signals so that all of the data is sampled at the above frequency. But, the EMI at the data bus becomes more problematic as the transmission frequency of the video data becomes higher.
In order to overcome the above-mentioned problem, an LCD driving apparatus with a dual-bus driving system as shown in
FIG. 3
has been used. Referring to
FIG. 3
, in order to reduce the EMI that is generated when the video data is transmitted to the source drive ICs
16
, the LCD controller
14
is provided with first and second data buses. The LCD controller
14
outputs data RDo, GDo and BDo for the odd-numbered pixels into the source drive ICs
16
over the first data bus while outputting the data RDe, GDe and BDe for the even-numbered pixels into the source drive ICs over the second data bus. In other words, as shown in
FIG. 4
, the LCD controller
14
divides the RD, GD and BD data that is input externally into odd-numbered pixel data RDo, GDo and BDo and even-numbered pixel data RDe, GDe and BDe in order to output them for the source drive ICs simultaneously. Accordingly the frequency of the source clock signal SCLK and the data that is outputted from the LCD controller
14
is reduced to half of the input frequency, so that the EMI is reduced at the transmission lines that are between the LCD controller
14
and the source drive ICs
16
.
Referring to
FIG. 5
, there is shown a variation of the dual-block driving system of FIG.
3
. The LCD driving apparatus of the dual-block driving system as shown in
FIG. 5
has also been used in order to reduce the EMI at the data transmission lines. In
FIG. 5
, the LCD controller
18
also includes first and second data buses like the dual-bus driving system of
FIG. 3
to reduce the frequency of the source clock signal SCLK and the data to half of the input frequency. The LCD controller
18
of
FIG. 5
outputs the data RDo, GDo and BDo as input for the odd-numbered source drive ICs
20
o
over the first data bus while outputting the data RDe, GDe and BDe as input for the even-numbered source drive ICs
20
e
over the second data bus. In other words, referring to
FIG. 6
, the LCD controller
18
splits the input data RD, GD, and BD into RDo, GDo, and BDo and RDe, GDe, and BDe as input for odd and even source drive ICs, respectively. Accordingly, the frequency of the source clock signal SCLK and the data that is output from the LCD controller
18
is reduced to half of the input frequency so that the EMI is reduced at the transmission lines that are between the LCD controller
14
and the source drive ICs
16
.
However, according to the LCD driving apparatus of the conventional dual-bus and dual-block driving systems, the number of data lines is doubled as the clock and the data frequencies are halved. Further, the data is input synchronously and simultaneously to the data lines so that the EMI problem still exists in the LCD.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a data transmitting apparatus and method for minimizing the EMI that occurs during parallel data transmission by utilizing a phase difference technique.
A preferred embodiment of the present invention includes a plurality of data signal inputs, a clock signal input having a predetermined frequency, a controller that receives the plurality of data signal inputs and the clock signal input, wherein the controller divides the frequency of the clock signal input by a desired number and outputs a frequency-divided clock signal output, and the controller separates the plurality of data signal inputs and outputs a plurality of separated data signal outputs such that at least one of the separated data signal outputs has a phase that is different than another of the separated data signal outputs.
Another preferred embodiment of the present invention includes a plurality of data signal inputs, a clock signal input having a predetermined frequency, a controller that receives the plurality of data signal inputs and the clock signal input, wherein the controller divides the frequency of the clock signal input by a desired number and outputs a plurality of frequency-divided clock signal outputs, and the controller separates the plurality of data signal inputs and outputs a plurality of separated data signal outputs such that at least one of separated data signal outputs has a different phase than another of the separated data signal outputs, the clock signal outputs include a first clock signal output and a second clock signal output, the second cl
Kim Seong J.
Kim Yu Soong
Lee Hyun Chang
Birch & Stewart Kolasch & Birch, LLP
LG. Philips LCD Co. Ltd.
Mengistu Amare
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