Apparatus and method for translating voltages

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307446, 307455, H03K 14086, H03K 140175

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active

050702610

ABSTRACT:
An apparatus and method for translating voltages between logic levels is provided having an input section (11), a level shifter section (89) and an output section (137). Input section (11) provides two control voltages to the level shifter section (89) in response to an input signal provided at input terminal (12). Level shifter section (89) comprises two inverters coupled to the control voltages. One inverter comprises p channel field-effect transistor (90) and n channel field-effect transistor (98). Another inverter comprises p channel field-effect transistor (106) and n channel field-effect transistor (114). For each inverter, the channel of the p channel field-effect transistor is over twice as wide as the channel of the n channel field-effect transistors. Each transistor (90, 98, 106 and 114) conducts current in response to a control voltage being anywhere within the voltage range, such that outputs of the inverters transition quickly in reponse to a transition of the control voltages. Output section (137) generates an output signal in response to the inverter outputs.

REFERENCES:
patent: 4797579 (1989-01-01), Lewis
patent: 4839537 (1989-06-01), Ueno
patent: 4987324 (1991-01-01), Wong et al.
"High Performance BiCMOS 100k-Gate Array", Gallia et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 142-149.
"An 8-ns 256K BiCMOS RAM", Tamba et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, pp. 1021-1026.

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