Apparatus and method for translating logical addresses for virtu

Details Apparatus and method for translating logical addresses for virtu Apparatus and method for translating logical addresses for virtu

1992-07-06

1995-07-25

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, G06F 1200, G06F 1206

Patent

active

054370167

ABSTRACT:
An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a multi-processor field of a translation lookaside buffer (TLB) has a value indicating whether or not the entry corresponds to an area common among virtual processors. The MP field of the TLB is compared with contents of the multi-processor register, and a virtual processor field of the TLB is compared with contents of a virtual processor register. If the value coincides with the multi-processor field or if the value does not coincide with the multi-processor field and the value coincides with the virtual processor field, contents of an absolute address field of the TLB are input to an absolute address register. This increases the effective capacity and utilization of the TLB to avoid decreasing of performance of the virtual machines.

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