Apparatus and method for translating ECL signals to CMOS signals

Details Apparatus and method for translating ECL signals to CMOS signals Apparatus and method for translating ECL signals to CMOS signals

1990-09-21

1991-11-26

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, H03K 190175

Patent

active

050685511

ABSTRACT:
The present invention provides an ECL to CMOS level translation circuit which uses a dynamic, internally generated reference voltage to translate ECL level signals into CMOS level signals. The translator includes an input translation circuit which uses emitter-follower bipolar transistors for receiving and interpreting the ECL level signals and to generate the dynamic, internally generated reference potential, and an output circuit for outputting the CMOS signals.

REFERENCES:
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4748346 (1988-05-01), Emori
patent: 4755693 (1988-07-01), Suzuki et al.
patent: 4806799 (1989-02-01), Pelley, III et al.
patent: 4864159 (1989-09-01), Cornelissen
An 8-ns 1 Mbit ECL BICMOS SRAM with Double Latch . . . , IEEE Journal of Solid State Circuits, vol. 24, #5, Oct. 1989, Matsui et al.

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