Patent
1996-09-10
1999-03-09
Decady, Albert
395568, G06F 1134
Patent
active
058812245
ABSTRACT:
In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry. The adder circuitry is operable to determine the number of said match results that are asserted and to represent the number as a sum via a set of adder circuitry outputs. A counter having a set of adder circuitry inputs is coupled to adder circuitry outputs. The counter is operable to increment its count by the sum represented by the adder circuitry outputs. In further embodiments, a multiplexer is interposed between the adder circuitry and the counter. The multiplexer has a first set of inputs coupled to the adder circuitry outputs, and a second set of inputs coupled to a source of the value "1." The multiplexer is operable to present either the first or second inputs on its outputs responsive to a select signal. The multiplexer has its outputs coupled to the increment inputs of the counter.
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Brockmann Russell C.
Lesartre Gregg B.
Ranson Gregory L.
De'cady Albert
Hart Kevin M.
Hewlett--Packard Company
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