Apparatus and method for testing the interconnection between int

Details Apparatus and method for testing the interconnection between int Apparatus and method for testing the interconnection between int

1993-01-21

1995-02-14

Beausoliel, Jr., Robert W.

Excavating

371 251, G01R 3128

Patent

active

053901916

ABSTRACT:
An integrated circuit for boundary scan is achieved to be simple structure. A testing apparatus 6 provides a testing data to a serial input port SI of a integrated circuit IC1 via a external terminal unit 2. The testing data is output to a parallel input port PI of the integrated circuit IC2 from a parallel output port SO of the integrated circuit IC1, then the testing data is output from the serial output port SO. The testing apparatus 6 compares with the testing data outputted to the integrated circuit IC1 and the testing data outputted from the integrated circuit IC2 so that a state of connection is detected between the parallel output port PO of the integrated circuit IC1 and the parallel input port PI of the integrated circuit IC2. The construction of the integrated circuits can be simplified by using both of inputting and outputting of the serial interface SIF.

REFERENCES:
patent: 4435806, Segers et al.
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patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 5056093 (1991-10-01), Wh et al.
patent: 5161160 (1992-11-01), Yaguchi et al.
IEEE Standard Test Access Port And Boundary-Scan Architecture, Published by the Institute of Electrical and Electronics Engineers, Inc., 345 East 47th St., New York, N.Y. 10017, USA, May 21, 1990.

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