Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-06-25
2004-07-13
Deb, Anjan K. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S537000, C324S763010, C365S201000, C714S736000
Reexamination Certificate
active
06762608
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor based memory devices, and in particular to testing fuses in integrated memory circuits.
BACKGROUND OF THE INVENTION
As the number of electronic elements contained on semiconductor integrated circuits continues to increase, the problems of reducing and eliminating defects in the elements become more difficult. To achieve higher electronic element population densities, circuit designers strive to reduce the size of the individual elements to maximize available die real estate, to increase speed of operation, to increase circuit density per chip, and the like. The reduced size of individual elements, however, makes these elements increasingly susceptible to defects caused by material impurities during fabrication. These defects can be identified upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective circuits is economically undesirable, particularly if only a small number of elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. To reduce the amount of semiconductor scrap, redundant elements are provided on the circuit. If a primary element is determined to be defective, a redundant element can be substituted for the defective element. Substantial reductions in scrap can be achieved by using redundant elements.
One type of integrated circuit device which uses redundant circuit elements is memory integrated circuits, such as, for example, dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), erasable programmable read only memories (EPROMs), synchronous dynamic random access memories (SDRAMs), FLASH memories, and other memory types. Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of memory cells are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced.
Because the individual primary circuit elements (rows or columns) of an integrated memory circuit are separately addressable, replacing a defective circuit element typically entails programming fuses to cause a redundant circuit element to respond to the address of the defective primary circuit element. This process is very effective for permanently replacing defective primary circuit elements.
In the case of DRAMs, for example, a particular memory cell is selected by first providing a unique row address of the row in which the particular memory cell is located and subsequently providing a unique column address of the column in which the particular memory cell is located. Redundancy circuitry must recognize the address of the defective primary circuit element and reroute all signals to the redundant circuit element when the address to the defective primary circuit element is presented by the user. Therefore, a number of fuses or antifuses are associated with each redundant circuit element. The possible combinations of programmed fuses corresponding to each redundant circuit element represent unique addresses of all primary circuit elements for which a corresponding redundant circuit element may be substituted. While antifuses are described, fuses will function equally as well in the circuit.
Antifuses are typically fabricated with a structure similar to that of a capacitor, such that two conductive electrical terminals are separated by a dielectric layer. In the unprogrammed state, in which the antifuse is fabricated, there is a high resistance between the terminals, while in the programmed state, there is low resistance. To program an antifuse, a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals.
All antifuses are tested to ensure that they are properly programmed. A prior art technique for testing antifuses is shown in
FIG. 1
, which shows two reference nodes, SGND node
10
and node
20
. The SGND node
10
is also in electrical communication with the input of a testing circuit, which is a comparator
30
which compares a hard wired reference voltage to the voltage on the SGND node
10
. A precharge voltage
40
is applied to the SGND node
10
. A switch
45
is interposed between precharge voltage
40
and SGND node
10
to turn the precharge voltage
40
on and off. The node
20
is connected to ground. Antifuses
50
are electrically interposed between the SGND node
10
and the node
20
.
Fuse F
1
is one of the fuses in bank B
1
. In order to test whether a good program has been achieved for fuse F
1
, switch SB
1
for the bank B
1
is actuated while switch SF
1
is enabled. Having both switch SB
1
and switch SF
1
simultaneously actuated creates a direct path from SGND node
10
to node
20
. Because the fuse F
1
has resistance and the bus to which it is connected has capacitance, upon actuation of both switch SB
1
and switch SF
1
, the voltage of SGND node
10
decays in a manner consistent with an RC circuit. Prior to the actuation of switch SB
1
and switch SF
1
, output of the comparator
30
is in a tri-state condition; however, as soon as switch SB
1
and switch SF
1
are actuated, the output of comparator
30
switches low. If fuse F
1
was properly programmed, the output of comparator
30
will switch back high at or before a switch time period t
fuse
. If the output of comparator
30
does not switch back high at or before switch time period t
fuse
, then fuse F
1
was not properly programmed.
The switch time period t
fuse
is typically determined by performing the following steps for a statistically valid number of fuses. First, the resistance of a fuse is measured. Techniques for measuring resistance are well known in the art; however, one way of measuring fuse resistance is by applying a voltage across a fuse, measuring the resulting current through the fuse, and calculating the resistance using Ohm's law. Second, a measurement is taken of the time it takes from when both the bank switch (such as, for example, SB
n
or SB
1
) and the fuse switch (such as, for example, SF
1
, SF
2
, SF
x
, etc.) are actuated for the output of the comparator
30
(as shown in
FIG. 1
) to swing to the high state. As an example, if fuse F
2
is being tested, both bank switch SB
1
and fuse switch SF
2
must be actuated. The measurement time obtained is referred to as a t
test
value. Third, the individual t
test
value for a particular fuse is plotted against the resistance value for such particular fuse, and this step is performed for all measured fuses. Fourth, a decision is made as to what resistance value is indicative of a fuse that has been programmed properly. For example, it may be decided that a resistance value of 300 K&OHgr; or less indicated that the fuse being tested has been properly programmed. Finally, from the plot of t
test
versus resistance, as described in the third step above, it is determined at or under which t
test
value the comparator output switched for a majority of the fuses measured having resistance values of 300 K&OHgr; or less.
The process of collecting and analyzing data for a statistically valid number of fuses can be lengthy. Accordingly, such process is performed offline. After data regarding fuse test times and resistance values are collected and analyzed, and a switch time period t
fuse
is established, individual fuses are then tested in accordance with the circuit shown in FIG.
1
. This testing is performed during manufacturing or as the fuses are programmed.
Moreover, the comparator
30
has a reference
55
which, in the prior art, is hardwired to a particular voltage value. Hence, the switch time period t
fuse
is highly dependent on the voltage value to which the reference in the comparator
30
is connected.
Byrd Phillip E.
Damon Tim
Deb Anjan K.
Schwegman Lundberg Woessner & Kluth P.A.
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