Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-10-09
2001-02-20
Saras, Steven J. (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C324S701000
Reexamination Certificate
active
06191770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a liquid crystal display for displaying a picture on a liquid crystal panel, and more particularly to a method and apparatus for testing a liquid crystal panel driving circuit. Also, this invention is directed to a testing circuit for testing a pixel matrix driving circuit.
2. Description of the Prior Art
Generally, a liquid crystal display apparatus displays a picture corresponding to video signals, such as television signals, on picture element (or pixel) matrices having pixels arranged in each intersection of gate lines and data lines. Each pixel consists of a liquid crystal cell for controlling a quantity of transmitted light in accordance with a voltage level of a data signal from the data line, and further consists of a thin film transistor(TFT) for switching the data signal to be transferred from the data line to the liquid crystal cell in response to a scan signal from the gate line. In order to drive the pixels, the liquid crystal display apparatus includes a data driving circuit for applying a data signal to each data line, and a gate driving circuit for applying a scan signal to the gate lines sequentially. These data driving circuit and gate driving circuit may have defects due to an error in the fabricating process. Typically, the liquid crystal display apparatus is provided with a redundant driving circuit used as a backup to a defective driving circuit.
For example, as shown in
FIG. 1
, the liquid crystal display apparatus provided with the redundant driving circuit includes a data driving circuit
4
connected to the data lines of a pixel matrix
2
, a gate driving circuit
6
connected to the left terminals of the gate lines and a redundant gate driving circuit
8
that can be serially connected to the right terminals of the gate lines. The gate driving circuit
6
includes
1
st to nth gate driving cells GD
1
to GDn that are connected to a start signal line SSL in series and to each of n gate lines. The first gate driving cell GD
1
includes a shift register
10
and a buffer
12
which are serially connected between the start signal line SSL and the left terminal of the first gate line GL
1
, and the respective second to nth gate driving cells GD
2
to GDn include a shift register
10
and a buffer
12
that are serially connected between two adjacent gate lines.
The gate driving cells GD
1
to GDn are sequentially enabled as a start voltage signal Vst from the start signal line is shifted, thus, sequentially driving the gate lines GL
1
to GLn. For example, the kth gate driving cell GDk drives the kth gate line GLk when a start voltage signal is applied from the (k-
1
)th gate driving cell. Likewise, the redundant gate driving circuit
8
includes 1st to nth redundant gate driving cells RGD
1
to RGDn that are serially connected to the start signal line SSL and, at the same time, connected to each of the n gate lines. The first redundant gate driving cell GD
1
includes a shift register
10
and a buffer
12
which can be serially connected between the start signal line SSL and the right terminal of the first gate line GL
1
. The respective 2nd to nth redundant gate driving cells RGD
2
to RGDn include a shift register
10
and a buffer
12
that can be serially connected between two adjacent gate lines. The redundant gate driving cells RGD
1
to RGDn drive the gate lines connected to the output terminals thereof when the start voltage signal Vst is shifted from the adjacent preceding gate lines. At this time, the first redundant gate driving cell RGD
1
receives the start voltage signal Vst from the start signal line SSL. For example, when the kth gate driving cell GDk has defects, the kth redundant gate driving cell RGDk is connected between the (k-
1
)th gate line GLk-
1
and the kth date line GLk by a manufacturer during fabrication, thereby driving the kth gate line GLk when the start signal Vst is input from the (k-
1
)th gate line GLk.
The test of such liquid crystal display apparatus should not only be repeatedly performed depending on the number of defective gate driving cells, but also should be alternated with the repair of gate driving cells having defects. For example, in the liquid crystal display apparatus described above and shown in
FIG. 1
, the test should be repeated at least three times when the third and (n-
2
)th gate driving cells GD
3
and GDn-
2
have defects. At the time of the first test, only the first and second gate lines GL
1
and GL
2
driven with the first and second gate driving cells GD
1
and GD
2
appear to be normal; while all of the third to nth gate lines GD
3
to GDn appear to be abnormal because of the defect in the third driving cell GD
3
. In other words, the 4th to nth gate lines GD
4
to GDn cannot be tested due to the defect in the third gate driving cell GD
3
. The second test is performed after the third redundant gate driving cell RGD
3
, instead of the third gate driving cell GD
3
, is set to the driving mode by the repair work of a manufacturer. At the time of the second test, the first to (n-
3
)th gate lines GLl to GLn-
3
appear to be normal; while the (n-
2
)th to nth gate lines GLn-
2
to GLn appear to be abnormal. In other words, the (n-
1
)th and nth gate lines GLn-
1
and GLn cannot be tested because the (n-
2
)th gate driving cell GDn-
2
is not operating properly. The abnormality of these (n-
1
)th and nth gate lines GLn-
1
and GLn can be detected through the third test. The third test is carried out after the second repair work, in which the (n-
2
)th redundant gate driving cell RGDn-
2
instead of the (n-
2
)th gate driving cell GDn-
2
is set to the driving mode, has been terminated. In the third test, all the first to nth gate lines GL
1
to GLn appear to be normal.
As described above, the conventional liquid crystal display apparatus provided with the redundant driving circuit was configured in such a manner that it was difficult to fully detect defects in the driving circuit with a single test. Because of this disadvantage in the conventional liquid crystal display apparatus provided with the redundant driving circuit, the testing and repairing work must be repeatedly performed depending on the number of defects in order to fully repair defects involved in the driving circuit. As a result, the conventional liquid crystal apparatus provided with the redundant driving circuit required a considerable time for testing and repairing. Also, the conventional liquid crystal display apparatus provided with the redundant driving circuit is problematic to a manufacturer because of the repeated testing and repairing depending on the number of defects.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for testing a driving circuit that is capable of performing a test of the driving circuit and a repair of defects in the driving circuit in a liquid crystal display.
In order to achieve this and other objects of the invention, a driving circuit testing method according to one aspect of the present invention includes a first step of applying a test signal to all the gate lines in parallel; a second step of applying the start signal to a first gate driving cell in the plurality of gate driving cells; a third step of allowing the signals to be latched into each gate driving cell; a fourth step of replacing the test signal being applied to the plurality of gate lines with the signals latched into the plurality of gate driving cells; and a fifth step of testing an enable state in each gate line.
A driving circuit testing method according to another aspect of the present invention includes a first step of applying a test signal to all the gate lines in parallel; a second step of applying the start signal to a first gate driving cell in the plurality of gate driving cells; a third step of allowing the signals to be latched into any ones of odd-numbered and even-numbered gate driving cells in the plurality of gate driving cells; a fourth step of replacing the signals l
Bell Paul A.
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Saras Steven J.
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