Apparatus and method for testing and verifying the refresh logic

Details Apparatus and method for testing and verifying the refresh logic Apparatus and method for testing and verifying the refresh logic

1983-07-05

1987-01-27

Heckler, Thomas M.

Boots, shoes, and leggings

364900, 365222, G06F 1300, G11C 700

Patent

active

046398589

ABSTRACT:
The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.

REFERENCES:
patent: 4006468 (1977-02-01), Webster
patent: 4142233 (1979-02-01), Suzuki
patent: 4158883 (1979-06-01), Kadono et al.
patent: 4204254 (1980-05-01), Muzzani et al.
patent: 4317169 (1982-02-01), Panepinto, Jr. et al.
patent: 4549284 (1985-10-01), Ikuzaki

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