Data processing: measuring – calibrating – or testing – Testing system – Including specific communication means
Reexamination Certificate
1999-02-09
2001-11-20
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Including specific communication means
C702S108000, C702S188000, C702S062000, C710S120000
Reexamination Certificate
active
06321174
ABSTRACT:
FIELD OF INVENTION
The present invention relates to an apparatus and method for testing a device, i.e. an add-on device of a computer system or an integrated circuit chip.
BACKGROUND OF INVENTION
After being manufactured, the functions of device, for instance, an add-on device of a computer system or an IC chip, is usually tested by a predetermined manner. The add-on device include the well known interface card.
A conventional approach to test an interface card is to install the interface card into a dedicated interface slot and to test whether the interface card operates as designed. However, to remove an interface card from the slot or insert an interface card into the slot of computer system, the operator must turn off the power to the computer system and the interface card first. After each interface card to be tested is inserted into the interface slot, the operator re-powers on the computer system. Afterwards, the computer system spends some times to do initialization. When a large amount of devices are required to test, it is evident that time-consuming power-on and initialization procedures of the computer system are involved in this conventional approach.
A test apparatus, illustrated in
FIG. 1
, was developed by Leap Corporation which allows the replacement of an interface card under continuous power-on condition of the computer system. The test apparatus
12
is attached to a first slot
11
on the computer system
10
. The test apparatus
12
includes a slot
17
for insertion of the interface card
18
to be tested and the slot
17
transmits the data/address lines
131
, the power lines
141
, and the reset line
151
of the second bus
171
. The test apparatus
12
further includes switch circuits
13
,
14
, and
15
each of which are respectively electrically connected to the slot
17
by the data/address lines
131
, the power lines
141
, and the reset line
151
. The switch circuits
13
,
14
, and
15
are respectively electrically connected to the first slot
11
by the data/address lines
112
, the power lines
113
, and the reset line
114
of the first bus
111
. As the switch circuit
13
is turned on by the control signal
191
from the switch button
161
, the data/address lines
112
on the first bus
111
make connection to the data/address lines
131
on the second bus
171
. As the switch circuit
14
is turned on by the control signal
192
from the switch button
162
, the power supplies on power lines
113
are applied to the power lines
141
of the second bus
171
. As the switch circuit
15
is turned on by the control signal
193
from the switch button
163
, the reset signal on the reset line
114
is transmitted to the reset line
151
of the second bus. On the contrary, as the switch circuit
13
is turned off, the data/address lines
112
on the first bus
111
are isolated from the data/address lines
131
on the second bus
171
. As the switch circuit
14
is turned off, the power lines
141
of the second bus
171
are cut off from the power supplies. As the switch circuit
15
is turned off, the reset signal does not appear on the reset line
151
of the second bus. In general, the first bus
111
and the second bus
171
are standard bus, such as ISA, EISA, PCI, and AGP, respectively.
The test can be accomplished with the assistance of three manually operated switch buttons
161
,
162
,
163
. During initial power-on, all switch buttons
161
,
162
,
163
are activated. When replacement of the interface card
18
under the test environment shown in
FIG. 1
is required, three manually operated switch buttons
161
,
162
,
163
are utilized to individually control the connection of the data/address signals, the power supplies and the reset signal. Therefore, in most conditions, the test apparatus provided by LEAP Corporation performs the function test efficiently. However, when the bus
111
,
171
involved are the PCI or AGP bus, the test apparatus
12
shown in
FIG. 1
is still inconvenient due to following reason. Different from an add-on device employing the EISA or ISA bus, an add-on device employing a PCI bus or AGP bus must be configured by the BIOS of the computer system
10
rather than the physical setup. Therefore, each time to test a PCI-type or AGP-type add-on device under the test environment shown in
FIG. 1
, the computer system
10
needs to reset and to re-configure the PCI-type or AGP-type add-on device. Besides, it is evident that the test procedures involved in the test apparatus
12
of
FIG. 1
cannot be automated due to the manually operated switch buttons
161
,
162
,
163
in the test apparatus
12
.
Accordingly, it is main objective of the invention to provide an apparatus and method for testing an add-on device or integrated circuit chip in an efficient way. The concept of this present invention is equally applicable to the test of an add-on device employing EISA, ISA, PCI, or AGP bus, etc.
SUMMARY OF INVENTION
The invention provides an apparatus for testing function of a device. The device includes the add-on device of a computer system, i.e. an interface card, and the IC chip. The apparatus communicates with the computer system via a first bus and communicates with the device via a second bus. The first and second buses are standard bus, e.g. EISA, ISA, PCI and AGP bus, etc.
According to the invention, the transmission of data/address signals, power signals and reset signal between the computer system and the device are enabled selectively and individually. Thereby, the test of the device can be accomplished without the time-consuming power on/off operation and re-initialization of the computer system. By a test program running in the computer system, the test of the device can also be accomplished automatically.
The first bus includes a multiple of data/address lines, power lines, and a reset line. The computer system includes an output port and a control program is executed in the computer system generating a plurality of control signals to the output port. The test apparatus includes a connection device, a first switch, a second switch, a third switch, a register and a control device.
The connection device makes connection of the second bus to the test apparatus. The first switch makes connection of the data/address lines of the first bus to the second bus while the first switch is switched on. The second switch makes connection of the power lines of the first bus to the second bus while the second switch is switched on. The third switch makes connection of the reset line of the first bus to the second bus while the third switch is switched on. The register is electrically connected to the output port for storing and outputting the plurality of control signals. The control circuit, responsive to the plurality of control signals, individually and selectively switches on the first, second and third switch.
According to the invention, an apparatus is provided for testing a device. The apparatus communicates with a computer system via a first bus which comprises a multiple of data/address lines, power lines, and a reset line. The apparatus communicates with the device via a second bus. The computer system comprises an output port, and a control program is executed in the computer system for generating a plurality of control signals to the output port. The apparatus comprises a connection device, a first switch circuit, a second switch circuit, a third switch circuit, a register, and a control circuit. The connection device functions to make connection of the second bus to the apparatus. The first switch circuit makes connection of the data/address lines of the first bus to the second bus while the first switch circuit is switched on. The second switch circuit makes connection of the power lines of the first bus to the second bus while the second switch circuit is switched on. The third switch circuit makes connection of the reset line of the first bus to the second bus while the third switch circuit is switched on. The register is electrically connected to the output port for storing and output
Chang Peter
Chen Jao-Ching
Yen Shu-Yi
Coudert Brothers
Hoff Marc S.
Tsai Carol S
Winbond Electronics Corp.
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