Apparatus and method for testing a memory array

Details Apparatus and method for testing a memory array Apparatus and method for testing a memory array

1995-10-06

1997-09-02

Nguyen, Hoa T.

Excavating

371 224, 365201, G01R 3128, G11C 700

Patent

active

056639651

ABSTRACT:
There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.

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