Apparatus and method for synchronizing symbol timing using...

Pulse or digital communications – Receivers – Automatic frequency control

Reexamination Certificate

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C455S182200, C455S192200

Reexamination Certificate

active

10722103

ABSTRACT:
A timing loop controller for multilevel modulation scheme is disclosed. The timing loop controller includes a first to fourth computing unit for computing a timing error between an input timing of digital signals and a sampling timing; a first to fourth quantization unit for controlling a direction and an error value of the timing error; a first and second sign detection unit for detecting sign change according to results; a zero crossing detection unit for detecting zero crossing at I axis and Q axis; and a timing error control unit for controlling the timing error value in case there is no sign change. The present invention can increase a zitter performance of timing error according to the signal-to-noise ratio by detecting the timing error, outputting the timing error and controlling the timing error output value only in case there is sign change by additionally equipping the sign variation detector.

REFERENCES:
patent: 5789988 (1998-08-01), Sasaki
patent: 5878088 (1999-03-01), Knutson et al.
patent: 6127897 (2000-10-01), Sasaki
patent: 6266377 (2001-07-01), Velez et al.
patent: 6278746 (2001-08-01), Velez et al.
patent: 6583822 (2003-06-01), Jun
patent: 6785074 (2004-08-01), Tsuchinaga
patent: 2001/0031020 (2001-10-01), Hwang et al.
patent: 2004/0095863 (2004-05-01), Verboom et al.
patent: 2000-55154 (2000-09-01), None
patent: 2002-64849 (2002-08-01), None
“The Performance of Symbol Timing Algorithm for Multi-level Modulation Scheme”, J. Song, et al., IEEE Vehicular Technology Conference, 1996, p. 1883-1887.
Floyd M. Gardner,A BPSK/QPSK Timing-Error Detector for Sampled Receivers,IEEE Trasnactions on Communications, Vol. Com. 34, No. 5, May 1986, pp. 423-429.
Seok Jun Ko et al.,A Robust Digital Timing Recovery with Asymmetry Compensation for High Speed Optical Drive Systems, IEEE Transactions on Consumer Electronics, vol. 47, No. 4, Nov. 2001, pp. 821-830.
“A Robust Digital Timing Recovery with Asymmetry Compensator for High Speed Optical Drive Systems”, S. Ko, 2001 IEEE, vol. 47, No. 4, Aug. 20, 2001, pp. 821-830.

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