Pulse or digital communications – Synchronizers
Reexamination Certificate
2000-10-27
2003-07-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
C375S371000, C327S152000, C327S153000, C327S161000
Reexamination Certificate
active
06594326
ABSTRACT:
BACKGROUND OF THE INVENTION
Today's complex digital systems contain storage devices, finite-state machines, and other such structures which control the movement of information by various clocking methods. Conversely, combinatorial logic devices, which are usually asynchronous, do not require time-based control signals for their operation. The output of an ideal combinatorial logic circuit is completely defined at any time by its inputs. In many digital circuits, however, it is expedient to cause the circuit's output to depend on both present and past inputs. Digital circuits whose outputs depend on such inputs are known as sequential circuits. A subset of this type of circuit is the synchronous sequential circuit, which requires a control signal to mark the passage of time and thereby delineate present inputs from past inputs. A clock signal serves this purpose, thereby controlling the transfer of digital information from one storage location to another.
An ideal clock signal is simply a periodic alternation between a logic high level and a logic low level. Typically, today's logic circuits use multi-phase clocks. Such clocking schemes may employ two-phase or four-phase clocks, or may use an even greater number of phases. The various phases are normally non-overlapping to prevent, as much as possible, race conditions and hazards, which commonly occur in digital circuits.
A hazard occurs when a circuit, under normal operating conditions, has the possibility of generating positive or negative pulses of possibly undefined duration at its output, when no such transitions should occur. This might occur, for example, where a designer fails to properly reduce logic terms. A race condition, on the other hand occurs when the output of a circuit is determined in part by which of two or more rising or falling edges is first received as an input to the circuit. Such a situation is normally avoided by synchronizing signals to a clock signal, meaning that the signals are related to the clock signal (and each other) in such a way that those signals may safely drive a circuit clocked by that clock signal. Such a race condition may result in a runt pulse at the circuit's output if no steps are taken to avoid it. Because a well-defined timing relationship is unlikely to exist between such input signals, neither the duration nor amplitude of a runt pulse is defined. One possible source of races is the improper distribution of clocking signals because the timing relationships involved become undefined.
Because modern digital systems are often very large, the number of devices driven by a clock may exceed the drive capabilities of the clock generation circuits, a common occurrence. In such a case, a clock signal will be distributed using one or more driver circuits because the clock circuit is unable to drive all of the devices directly. When using multiple clock drivers, the circuits being driven will be partitioned into logical subcircuits and the output of each clock driver used to drive those subcircuits. The signal propagation delays through each of the clock driver circuits will likely differ. The load presented to each drive circuit will also likely differ, also causing differences in the outputs of each clock driver circuit. These differences are known as clock skew.
Generally speaking, information transfer from a signal synchronized to a later clock to circuit elements clocked with an earlier clock will function correctly. However, a transfer of information from an earlier clock to a later clock may encounter problems. For example, if two flip-flops are connected serially with the first flip-flop providing input to the second flip-flop, the circuit should function as a shift register. If two separate clocks are provided, one to each flip-flop, and the second flip-flop is clocked simultaneously with or before the first flip-flop, both flip-flops may be loaded with the same data, and thus fail to function as a shift register. In such cases, the two clocks must be synchronized in some way.
Similarly, outputs from a first digital circuit operating using a first clock which are taken as input by a second digital circuit operating on a second clock must often be synchronized to the second clock. This is also true of asynchronous inputs generated by a user, sensors, or other such input sources.
FIG. 1
illustrates several of the proceeding concepts.
FIG. 1
shows a clock enable signal rclk_en
100
generated by a control signal receiver
102
from a bus control input
104
(received from a bus (not shown)). Clock enable signal rclk_en
100
enables the generation of a clock rclk
110
. A bus clock
112
is also received from the bus. Bus clock
112
is provided to a phase detector
114
and a delay-locked loop
116
. Phase detector
114
compares bus clock
112
with a clock mclk
120
, which also clocks control signal receiver
102
. Phase detector
114
generates a phase difference signal
122
that represents the difference in phase between bus clock
112
and mclk
120
. Delay-locked loop
116
generates a master clock dllclk
130
by variably delaying bus clock
112
. Delay-locked loop
116
uses phase difference signal
122
to set the amount of delay necessary to keep mclk
120
synchronous with bus clock
112
.
The circuit of
FIG. 1
operates in the following manner. Clock dllclk
130
is fed into a inverter
132
which drives a first NAND gate
134
and a second NAND gate
136
. The second input of first NAND gate
134
is tied high to voltage VDD
160
, causing the output of first NAND gate
134
to follow the input of inverter
132
. First NAND gate
134
outputs a delayed version of dllclk
130
, which then passes through an inverter string
140
and emerges as mclk
120
. Similarly, second NAND gate
136
drives an inverter string
150
and emerges as rclk
110
. Inverter string
150
serves as a clock driver circuit, allowing rclk
110
to drive large numbers of devices.
The function of second NAND gate
136
is to disable rclk
110
. The function of first NAND gate
134
is to maintain equality in the delays experienced in generating rclk
110
and mclk
120
. Because the delay experienced in generating rclk
110
from dllclk
130
is equal to that experienced in generating mclk
120
from dllclk
130
, rclk
110
is synchronous with mclk
120
, save for the fact that rclk
110
is not generated until enabled by rclk_en
100
. So long as the delays in generating rclk
110
and mclk
120
are kept equal, other devices may therefore be used in place of first NAND gate
134
and second NAND gate
136
, such as NOR gates or tristable devices. However, the delays experienced in generating rclk
110
from dllclk
130
should always be identical to those experienced in generating mclk
120
. Because the phase delay experienced in generating mclk
120
from dllclk
130
is defined (i.e., the delay is calculable and/or measurable, although it may not be known), a substantially quantifiable phase relationship exists between mclk
120
and dllclk
130
. An example of a delay-locked loop receiver is described in U.S. patent application Ser. No. 08/795,657 entitled “DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT,” having as inventors Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark Johnson, Benedict Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, and Donald Stark, and assigned to Rambus, Inc., the assignee of the present invention, and is hereby incorporated by reference in its entirety.
FIG. 2A
illustrates the waveforms which may be generated by the operation of the circuit illustrated in FIG.
1
. Throughout this discussion, references to a signal or element of a preceding figure will use the original reference numbers. Moreover, idealized signal waveforms will be used to simplify the discussion. As illustrated in
FIG. 2A
, the waveform of dllclk
130
is a square wave having a 50% duty cycle and a period of (T
3
-T
0
). As is shown in
FIG. 2A
, rclk
110
and mclk
120
of
FIG. 1
are simply delayed versions o
Dillion Nancy David
Dillon John B.
Portmann Clemenz
Dillion Nancy David
Ha Dac V.
Pennie & Edmonds LLP
Rambus Inc.
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