Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2002-04-12
2004-09-21
Bayard, Emmanuel (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
Reexamination Certificate
active
06795510
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to symbol timing recovery detectors and more particularly to digital symbol timing recovery detectors for use in multi-level symbol transmission systems.
BACKGROUND OF THE INVENTION
Digital data communications systems transmit digital data via signals representing successive symbols, each symbol representing a predetermined number of bits, separated by a predetermined time interval. In order to properly receive the transmitted digital data, the timing of the symbols must be recovered. Early symbol timing recovery (STR) detectors were based upon an analog continuous-time techniques. Development of digital data systems led to a corresponding development of sampled data/digital STR detectors.
Mueller and Muller (M&M) developed such a sampled data STR detector that required one sample per data symbol and decision-directed operation. However, in a carrier-type transmission system the M&M STR detector requires prior acquisition of carrier phase for proper operation. The M&M STR detector can operate successfully in a multilevel symbol transmission system, such as an xVSB or xQAM system. However, because the M&M detector is decision-directed, the symbol timing recovery loop will not lock to a signal when the baseband data is so distorted that an accurate decision cannot be made. While an equalizer can correct for these conditions, such equalizers require that the symbol timing be accurate and stable, and are located downstream of the STR detector.
Gardner later developed a sampled data/digital STR detector for bilevel modulation systems, such as BPSK or QPSK.
FIG. 1
is a block diagram of the known Gardner STR detector and
FIG. 2
is a waveform diagram and table useful in understanding the operation of the Gardner STR detector. In
FIG. 1
, the sampled input signal IN from a signal sampler (not shown) is coupled to an input terminal of a first delay circuit
102
, and a first input terminal of a subtractor
106
. An output terminal of the first delay circuit
102
is coupled to an input terminal of a second delay circuit
104
and a first input terminal of a multiplier
108
. An output terminal of the second delay circuit
104
is coupled to a second input terminal of the subtractor
106
. An output terminal of the subtractor
106
is coupled to a second input terminal of the multiplier
108
. An output terminal of the multiplier generates a phase error representative signal ERR. The error signal ERR is coupled to a control input terminal of a timing signal generator (not shown) which, in turn, controls the timing of the samples taken by the signal sampler and supplied to the input terminal IN of the STR detector. A sample clock signal from the timing signal generator is coupled to clock input terminals of the first and second delay circuits
102
and
104
.
In
FIG. 2
, the horizontal axis represents time, and the vertical axis represents the value of the input signal and of the samples representing that signal. In
FIG. 2
, the waveform
110
represents the received analog signal. The samples of the sampled input signal IN, produced by the signal sampler, are represented by circled dots along the waveform
110
. The waveform
110
is illustrated as linear between symbols, though one skilled in the art will understand that this is not necessarily true in actual systems.
As described above, the generation of the samples is synchronized to a sample clock, generated by a sample clock generating circuit (not shown), the phasing of which is controlled by the error signal ERR generated by the STR detector illustrated in
FIG. 1
, all in a known manner. Sample times are illustrated by thin vertical lines below the waveform
110
. The horizontal location of these vertical lines represents the sample times. As is known, the Gardner STR circuit requires two samples per symbol, one sample of which represents the symbol value. Those samples representing the symbols are represented by thin vertical lines above the waveform
110
. Symbol time samples (e.g. t
1
, t
3
, t
5
, etc.) alternate with transition time samples (t
2
, t
4
, t
6
, etc.).
In the table
112
beneath the waveform diagram, each row represents the values of the samples in a respective one of the sample streams illustrated in FIG.
1
. Each column represents the state of that signal at the corresponding time of the sample illustrated along the waveform
110
. That is, the first column represents the sample values at time t
1
, the second column represents the sample values at time t
2
and so forth.
In operation, the first and second delay circuits,
102
and
104
, are clocked by the sample clock from the sample clock signal generator (not shown). The sample Va at the input terminal IN, from the sampler (not shown), supplied to the first delay circuit
102
, is assumed to be the latest symbol time sample. The top row of the table
112
illustrates the value of the samples Va. The sample Vb at the output terminal of the first delay circuit
102
is delayed by one sample period from the sample Va, and represents the last preceding transition time sample. The second row of the table
112
illustrates the value of the samples Vb. The sample Vc at the output terminal of the second delay circuit
104
is delayed by one sample period from the sample Vb and by two sample periods from the sample Va, and represents the last preceding symbol time sample. The third row of the table
112
illustrates the value of the samples Vc.
In general, the value of the transition sample represents the degree of phase error. That is, if the phase of the sample clock is aligned properly with the symbols in the received signal, the transition sample will be zero. If the transition sample is not zero, this indicates a phase error. The further the transition sample is from zero (either positive or negative), the greater the phase error of the sampling clock.
The slope of the signal between the preceding and succeeding symbol time sample provides the indication of whether the sampling is early or late. If the slope is negative, indicating a transition from a high value to a low value, and the transition sample is positive, this indicates early sampling, and the resulting error signal ERR conditions the sample clock signal generator to retard the phase of the sampling clock signal. In the illustrated embodiment, the error signal is positive to indicate early sampling. If the slope is negative and the transition sample is negative, this indicates late sampling, and the resulting error signal conditions the sample clock signal generator to advance the phase of the sampling clock signal. In the illustrated embodiment, the error signal is negative to indicate late sampling.
Conversely, if the slope is positive, indicating a transition from a low value to a high value, and the transition sample is positive, this indicates late sampling, and the resulting error signal (negative) ERR conditions the sample clock signal generator to advance the phase of the sampling clock signal. If the slope is positive and the transition sample is negative, this indicates early sampling, and the resulting error signal (positive) conditions the sample clock signal generator to retard the phase of the sampling clock signal.
Gardner represents the polarity of the slope of the input signal
110
between adjacent symbol times, Va and Vc, by the difference Vc−Va between the surrounding symbol samples, Va and Vc. Gardner sets the value of the error signal ERR to be the product of the transition sample multiplied by the polarity, i.e. ERR=Vb·(Vc−Va). This value is valid only at sample times, and is illustrated in table
112
by depicting the transition times as being crosshatched.
In
FIG. 2
, the sample timing is assumed to be properly aligned with the symbol timing of the received signal
110
. If there is a symbol transition, and the transition time sample is zero, this indicates that the symbol timing is correct and the error value product, described above, is zero. This is illustrated in
FIG. 2
at times t
3
, t
Bayard Emmanuel
Kurdyle Ronald H.
Laks Joseph J.
Thomson Licensing S.A.
Tripoli Joseph S.
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