Apparatus and method for switching clocks while preventing...

Details Apparatus and method for switching clocks while preventing... Apparatus and method for switching clocks while preventing...

2005-10-19

2010-02-16

Odom, Curtis B (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S354000, C713S322000

Reexamination Certificate

active

07664212

ABSTRACT:
A apparatus (700) and method (600) are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion (110) of an Ultra Wideband (UWB) receiver. a first and a second recovered clock (111, 112) and an external clock (109) can be input to a switch (116). Logical rules (490) can be used to determine conditions under which to hold the state of an output clock (310, 320) based on the states of a first clock (410, 420, 430, 440) and a second clock (450, 460, 470, 480) and the state of a switch request signal (312). In addition to holding the state of the output clock, a first data stream (501) associated with the first clock and a second data stream (502) associated with the second clock can be synchronized such that when switching from the first to the second clock no data loss will be experienced in the data stream.

REFERENCES:
patent: 6618455 (2003-09-01), Maeda et al.
patent: 6639449 (2003-10-01), De La Cruz et al.
patent: 7366091 (2008-04-01), Lahti et al.
patent: 2006/0274815 (2006-12-01), Joseph

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