Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2005-08-30
2005-08-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C327S161000, C331S011000
Reexamination Certificate
active
06937077
ABSTRACT:
A clock synchronization circuit (200, FIG.2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.
REFERENCES:
patent: 4805021 (1989-02-01), Harlos et al.
patent: 5781054 (1998-07-01), Lee
patent: 5889435 (1999-03-01), Smith et al.
patent: 5923715 (1999-07-01), Ono
patent: 6037812 (2000-03-01), Gaudet
patent: 6087868 (2000-07-01), Millar
patent: 6137328 (2000-10-01), Sung
patent: 6215726 (2001-04-01), Kubo
patent: 6222895 (2001-04-01), Larsson
patent: 6259288 (2001-07-01), Nishimura
patent: 6292040 (2001-09-01), Iwamoto et al.
patent: 6337590 (2002-01-01), Millar
patent: 6359487 (2002-03-01), Heightley et al.
patent: 6373913 (2002-04-01), Lee
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6489823 (2002-12-01), Iwamoto
patent: 6522122 (2003-02-01), Watanabe et al.
Gomm Tyler J.
Zarate Oliver F.
Callahan Timothy P.
Luu An T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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