Apparatus and method for summing 1-bit signals

Details Apparatus and method for summing 1-bit signals Apparatus and method for summing 1-bit signals

1997-11-26

1999-11-09

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 750

Patent

active

059832584

ABSTRACT:
An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 together with columns A and B is the truth table of an NAND gate. Column b.sub.2 together with columns A and B is the truth table of a COINCIDENCE gate.
In the example of FIG. 5 column b.sub.4 equals B; column b.sub.1 is logical 0 whatever the states of A and B; and column b.sub.5 is NOT A.
Thus in accordance with one illustrative embodiment of the invention the arithmetic stage 40 may be implemented by the logic circuit of FIG. 6 where

REFERENCES:
patent: 4357674 (1982-11-01), Ikeda et al.
patent: 5442577 (1995-08-01), Cohen
patent: 5796645 (1998-08-01), Peh et al.

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