Apparatus and method for successive approximation...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S155000

Reexamination Certificate

active

07898453

ABSTRACT:
A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

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International Search Report - PCT/US09/066881 - International Search Authority, European Patent Office, Jun. 29, 2010.
Van Elzakker M. et al., “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC” Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, IEEE, Piscataway, NJ, USA, Feb. 3, 2008, pp. 244-610.

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