Registers – Systems controlled by data bearing records – Time analysis
Patent
1976-09-29
1978-02-07
Atkinson, Charles E.
Registers
Systems controlled by data bearing records
Time analysis
G11C 2900, G06F 1112
Patent
active
040728536
ABSTRACT:
Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.
REFERENCES:
patent: 3766521 (1973-10-01), Carter et al.
patent: 3814921 (1974-06-01), Nibby et al.
patent: 3836957 (1974-09-01), Duke et al.
patent: 3949208 (1976-04-01), Carter
patent: 4005405 (1977-01-01), West
Barlow George J.
Nibby, Jr. Chester M.
Atkinson Charles E.
Driscoll Faith F.
Honeywell Information Systems Inc.
Prasinos Nicholas
Reiling Ronald T.
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