Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-06-15
2004-03-23
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S412000, C370S474000
Reexamination Certificate
active
06711165
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to layer
2
and layer
3
switching of data packets in a non-blocking network switch configured for switching data packets between subnetworks.
BACKGROUND ART
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full-duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer
2
type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1q protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer
2
level, a router is typically necessary to transfer the data packet between subnetworks.
Efforts to enhance the switching performance of a network switch to include layer
3
(e.g., Internet protocol) processing may suffer serious drawbacks, as current layer
2
switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the switch at the same rate that the data packets are received. Newer designs are needed to ensure that higher speed switches can provide both layer
2
switching and layer
3
switching capabilities for faster speed networks such as 100 Mbps or gigabit networks.
However, such design requirements risk loss of the non-blocking features of the network switch, as it becomes increasingly difficult for the switching fabric of a network switch to be able to perform layer
3
processing at the wire rates (i.e., the network data rate).
SUMMARY OF THE INVENTION
There is a need for an arrangement that enables a network switch to provide layer
2
switching and layer
3
switching capabilities for 100 Mbps and gigabit links without blocking of the data packets.
There is also a need for an arrangement that enables a network switch to provide layer
2
switching and layer
3
switching capabilities with minimal buffering within the network switch that may otherwise affect latency of switched data packets. There is also a need for an arrangement that enables a network switch to be easily programmable to distinguish between different types of layer
3
data packets, wherein the network switch can interact with the host processor in loading min terms, used in evaluating layer
3
data packets, into specialized memories within a network switch port.
There is also a need for an arrangement that minimizes required memory space in a network switch port by optimizing the storage of min terms, used in evaluating layer
3
data packets, for evaluation of the most relevant data bytes of the layer
3
data packets.
These and other needs are attained by the present invention, where min terms to be used in evaluating an incoming data packet are stored in a network switch port based on min term relevance to the received data bytes and memory block capacity. The method includes receiving from a host controller a plurality of templates configured for simultaneous identification of respective data formats in the incoming data packet. Each template has at least one min term configured for comparing a corresponding prescribed value to a corresponding selected byte of the incoming data packet. The method also includes allocating memory block sizes based on relevance of respective incoming data bytes of the incoming data packet to evaluation of the incoming data packet, and storing the min terms in a min term memory within the network switch port. The storing of min terms includes storing a first group of the min terms configured for simultaneous comparison with a corresponding first of the incoming data bytes in a first memory block within the min term memory, and storing a first excess group of the first group of min terms configured for simultaneous comparison with the corresponding first of the incoming data bytes in a user-defined memory block within the min term memory in response to the first group of min terms exceeding a capacity of the first memory block. The storage of templates configured for identifying respective data formats enables the network switch port to be easily programmable to identify user-defined data formats. Moreover, the storage of the relevant min terms in memory blocks over at least two allocated memory blocks enables the memory to be optimized for access and capacity to store the most relevant min terms.
Another aspect of the present invention provides for a network switch port. The network switch port includes a processor interface configured for receiving a plurality of templates configured for simultaneous identification of respective data formats in an incoming data packet. Each template has at least one min term configured for comparing a corresponding prescribed value to a corresponding selected byte in the incoming data byte. The network switch also includes a min term memory configured for storing min term values and having a plurality of memory blocks. Each min term value is stored in a selected memory block, having a corresponding size, based on at least one of a location of a corresponding selected byte of the incoming data packet for comparison and a relevance of the corresponding selected byte to evaluation of the incoming data packet. The network switch port filter also includes a min term controller configured for allocating memory block sizes in the min term memory based on relevance of respective incoming data bytes of the incoming data packet for evaluation of the incoming data packet. The min term controller stores a first group of the min terms configured for simultaneous comparison with a corresponding first of the incoming data bytes in a first memory block within the min term memory. The min term controller also stores a first excess group of the first group of min terms configured for simultaneous comparison with the corresponding first of the incoming data bytes in a user-defined memory block within the min term memory. Hence, the storage of relevant min terms may be organized according to location of the corresponding selected byte of the selected incoming data byte, optimizing the min term memory for access and capacity.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
REFERENCES:
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6021132 (2000-02-01), Muller et al.
patent: 6389468 (2002-05-01), Muller et al.
patent: 6453360 (2002-09-01), Muller et al.
Advanced Micro Devices , Inc.
Kizou Hassan
Manelli Denison & Selter PLLC
McLoughlin Michael I.
Turkevich Leon R.
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