Boots – shoes – and leggings
Patent
1992-11-09
1994-07-05
Chan, Eddie P.
Boots, shoes, and leggings
395575, 395700, 364DIG1, 3642802, 3642665, 3642689, 3642692, 364961, 364944, 36494461, 36494492, 364945, G06F 1100, G06F 1200
Patent
active
053275489
ABSTRACT:
A system and method for managing spare bit steering information in a multi-processor system having a global/local memory architecture. During the system boot cycle one of the multiple processors is selected to test global memory and to configure the steering of the spare bits by bank or the like. Each processor tests its own local memory and defines the associated spare bit steering for the local memory. The global memory spare bit steering configuration information, as well as other global memory configuration information, in the selected processor is distributed to the other processors using registers in a commonly accessible atomic semaphore controller or through a commonly accessible block of global memory. Preferably, the selection of the processor to test the global memory is performed so that no single processor always has the responsibility. In this way, the acquisition of global memory spare bit steering information is not linked to the operative status of any one processor.
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Hardell, Jr. William R.
Henson, Jr. James D.
Mitchell Oscar R.
Chan Eddie P.
International Business Machines - Corporation
Salys Casimer K.
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