Apparatus and method for stacking integrated circuit devices

Details Apparatus and method for stacking integrated circuit devices Apparatus and method for stacking integrated circuit devices

1993-12-03

1995-10-03

Vo, Peter

Metal working

Method of mechanical manufacture

Electrical device making

29740, 29827, 29830, 22818022, 257737, 257774, 257778, 439 65, H05K 334, H01L 23495, H01R 909

Patent

active

054541603

ABSTRACT:
An apparatus and method for stacking integrated circuit devices which combine flip-chip technology and soldering methods with laminated stack frames to provide a vertical stack array with minimal parasitic inductance. Each laminated stack frame has a central cavity and includes a plurality of vias extending through them. The vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump. Each laminated stack frame also includes a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a flip-chip integrated circuit chip, and a plurality of traces coupling each solder bump pad to a via. The bottom surfaces of the vias of a bottom laminated stack frame couple to contacts on a printed circuit board.

REFERENCES:
patent: 3868765 (1975-03-01), Hartleroad et al.
patent: 3914850 (1975-10-01), Coucoulas
patent: 3984860 (1976-10-01), Logue
patent: 4021838 (1977-05-01), Warwick
patent: 4079509 (1978-03-01), Jackson et al.
patent: 4774760 (1988-10-01), Seaman et al.
patent: 4801992 (1989-01-01), Golubic
patent: 4825284 (1989-04-01), Soga et al.
patent: 4954878 (1990-09-01), Fox et al.
patent: 5019673 (1991-05-01), Juskey et al.
patent: 5046953 (1991-09-01), Shreeve et al.
patent: 5058265 (1991-10-01), Goldfarb
patent: 5065227 (1991-11-01), Frankeny et al.
patent: 5072289 (1991-12-01), Sugimoto et al.
patent: 5103290 (1992-04-01), Temple et al.
patent: 5111279 (1992-05-01), Pasch et al.
patent: 5168346 (1992-12-01), Pasch et al.
patent: 5173574 (1992-12-01), Kraus
patent: 5191511 (1993-03-01), Sawaya
patent: 5219377 (1993-06-01), Poradish
Direct Light-Chip Interconnection Scheme Accommodating Flip-Chip Bonding; IBM Technical Disclosure Bulletin, vol. 33, No. 8; Jan. 1991; pp. 141-142.

Affiliated with

Also associated with

Rating

Apparatus and method for stacking integrated circuit devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for stacking integrated circuit devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for stacking integrated circuit devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1070971