Apparatus and method for simultaneously presenting error interru

Details Apparatus and method for simultaneously presenting error interru Apparatus and method for simultaneously presenting error interru

1988-06-30

1993-11-30

Baker, Stephen M.

Excavating

371 18, 395575, G06F 1130

Patent

active

052672468

ABSTRACT:
Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.

REFERENCES:
patent: 3930146 (1975-12-01), Bogacz
patent: 4549256 (1985-10-01), Castel et al.
patent: 4627054 (1986-12-01), Cooper et al.
patent: 4701845 (1987-10-01), Andreason et al.
patent: 4868818 (1989-09-01), Madan et al.
Slater, M., Microprocessor-Based Design, 1987, Mayfield pub., pp. 124-126, 441-449.
Goolsbey, M. et al., "Machine Check Processing by Vectors", IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2472-2479.
IBM Tech. Disclosure Bull., vol. 20, No. 3, Draper et al., "Program Service Underrun Detection", Aug. 1977, pp. 1144-1145.
IBM Tech. Disclosure Bull., vol. 20, No. 4, Oliver et al., "Support Processor Error Recovery", Sep. 1977, pp. 1362-1365.
IBM Tech. Disclosure Bull., vol. 22, No. 2, Dodge, "Channel Adapter", Jul. 1979, pp. 753-754.
IBM Tech. Disclosure Bull., vol. 25, No. 10, Bhansali et al., "Recovery Mechanism for . . . Communications Between a Data Processor and an I/O . . . ", Mar. 1983, pp. 5226-5229.
IBM Tech. Disclosure Bull., vol. 27, No. 2, Castel, "Communication Scanner Error Reporting", Jul. 1984, pp. 1154-1155.
Communications of the ACM, vol. 28, No. 1, Seitz, "The Cosmic Cube", Jan. 1985, pp. 22-33.
Proc. Int'l. Conf. on Parallel Processing, 1985, Tuazon et al., "Caltech/JPL Mark II Hypercube Concurrent Processor", pp. 666-673.
Computer Design, Falk, "Computing Speeds Soar with Parallel Processing", Jun. 15, 1988, pp. 49-58.

Affiliated with

Also associated with

Rating

Apparatus and method for simultaneously presenting error interru does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for simultaneously presenting error interru, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for simultaneously presenting error interru will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2103430