Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-03-31
1999-10-26
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 34, 712 35, G06F 1312, G06F 720, G06F 944
Patent
active
059745215
ABSTRACT:
An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare operation and the I/O buffer register memory cells perform at least one write operation.
REFERENCES:
patent: 4580215 (1986-04-01), Morton
patent: 5343559 (1994-08-01), Lee
Friedman Mark M.
Neomagic Israel Ltd.
Pan Daniel H.
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