Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2000-07-13
2001-11-13
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S012000
Reexamination Certificate
active
06316966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, generally, to apparatus and methods of phase detection, and, in particular embodiments to methods and apparatus for high speed phase detection and clock regeneration in which variable circuit delays are inserted into phase detector circuitry and controlled by feedback loops in order to adjust signal propagation times.
BACKGROUND OF THE INVENTION
As the demand for data bandwidth increases, so does the demand for high bandwidth optical data transmission techniques.
Typically, there are two basic ways that digital data is formatted in fiber optic systems. The two formats are the return-to-zero (RZ) format and the non-return-to-zero (NRZ) format. In the NRZ format, each bit of data occupies a separate timeslot and is either a binary 1 or a binary 0 during that time period. In contrast, in the RZ format, a time period is allowed for each bit. Each bit is transmitted as a pulse or an absence of a pulse. Both formats are referenced to a system clock. The system clock, however, is not a separate signal and must be recovered from the data. A clock signal may be recorded, for instance from NRZ data, by using the transition occurrences within the data transmitted. The process of recovering a clock signal from transmittal data is typically referred to as clock data recovery (CDR). Clock data recovery subsystems are a key block for digital communications and telecommunication circuits. CDR systems are also used in a variety of other digital systems, for example disk drives.
Commonly clock data recovery circuits are based on the use of phase lock loops (PLL). Unlike phase lock loops that are used in wireless applications, a CDR PLL operates on random data, such as but not limited to non-return-to-zero data, instead of a sine wave or modulated sine wave signal. With NRZ data, the clock signal, which is encoded with the data, must be regenerated from the data since the data must eventually be processed synchronously. A further complication with clock and data recovery circuits is that the data spectrum is broadband. This is in contrast to the narrow band spectrum PLLs, which are commonly encountered in typical PLL applications such as synthesizers, demodulators, and modulators.
In CDR circuits, a regenerated clock signal is typically used to retime the data through a Flip-Flop, which is used as a decision circuit. This retiming of data comprises the data recovery function of the CDR circuit. By retiming the data, the data stream is essentially recreated and time domain jitter, which may be present in the NRZ signal or produced by the NRZ receiver circuitry, may be greatly reduced.
A typical application using clock and data recovery circuits is a SONET (synchronous optical network) system. In SONET systems, the CDR subsystem has difficult performance specifications to meet in terms of jitter tolerance, jitter generation, jitter transfer, bit error rate, and phase margin. These performance specifications are held within tight tolerances so that SONET systems may deliver high quality data with a low BER (bit error rate).
A key parameter affecting the quality of data received is the phase margin. Phase margin is the phase relationship between data and clock that results in correct data being reproduced. In other words, if the phase margin of a decision circuit that is decoding the transmitted data needed is exceeded, the probability that errors can result may increase. In order to minimum phase margin error, the clock should cause the data to be sampled at times when the data is stable, that is, at a time when the data is not in transition. Such sampling requires that the sampling edge of the clock signal reside at or near the middle of the transmitted data bit. This condition, in which the clock resides in the middle of the data bit, is referred to as centered clock/data. To achieve the condition of centered clock/data the phase lock loop within the clock and data recovery circuit must maintain a particular static phase offset between the clock and data. This static phase offset requirement is typically more stringent than the lock requirement in standard PLL applications. In addition, because the clock regeneration is using a data stream to regenerate the clock, the performance of the phase detector will be dependent on the data patterns within the data transmitted.
Commonly Hogge type phase detectors are used in clock data recovery circuits. Process, temperature, voltage, data pattern, transition density, and matching circuit delay variations affect the performance of Hogge type phase detectors. Such variations, which are difficult to compensate, result in a combination of increased static phase error, reduced phase margin, and high pattern dependant jitter. In high-speed designs, the effect of such variations is exacerbated. Accordingly, design issues become more critical for proper circuit operation as data rate increases.
SUMMARY OF THE DISCLOSURE
Accordingly, to overcome limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading the present specification, preferred embodiments of the present invention relate to apparatus and method for assuring proper phase margin, in order to achieve high rates of reliable data reproduction.
A preferred embodiment of the present system comprises the integration of Hogge and Alexander type phase detectors.
In particular, preferred embodiments of the present system provide a linear type phase detector, exemplary a Hogge type phase detector. The linear phase detector has matching delays inserted within the circuitry within the data and/or clock paths to compensate for mismatch in the different propagation speeds of data and clock signals through the circuitry.
Signal propagation through circuitry changes with a variety of variables such as the process used to fabricate the circuit, actual fabrication parameters, temperature, voltage, input signal level and even the data pattern received. Because a variety of variables affect propagation delays, it is very difficult to match propagation delays statically through clock and data circuits. It is important to match clock and data propagation times through circuitry because the maximum data frequency can be achieved if the transition times for the data and clock are matched. In order to match the propagation delays of the data and clock signals through circuitry variable circuit delays are placed in the clock and/or data path. The phase mismatch between the data and clock is measured locally using a digital phase detector also known as a “bang-bang” phase detector. Once the phase difference between the clock and data is determined, a delay upstream of the clock and/or data signal can be controlled in order to match propagation delays and hence the phase of the data and clock signals.
Because the factors affecting propagation delay within a circuit change slowly, the control loops used to control the propagation delays within the circuitry must be low bandwidth. Additionally the control loop bandwidth should be low so that control loops for the inserted circuit delays not react to transitory upsets in data or clock signals. The local matching control loop should be significantly slower than the overall phase detector loop. In practice, slowing the local control loop is problematical. The traditional method of slowing the response of a control loop, such as an AFC loop, is to add an integrator with a large time constant. Such large time constants are traditionally accomplished by inserting a RC (Resistor-Capacitor) network with a large time constant. Such a large time constant can be fabricated by adding external resistors or capacitors to the phase detector circuitry, which is contained in an integrated circuit. Adding such external components not only adds to the cost of the circuitry, but also consumes precious input/output pins upon the integrated circuit containing the loop.
In one embodiment of the present invention, a method, which may accomplish the same purpose as the large time constant RC net
Beccue Steven
Chang Charles
Lao Zhihao
Petersen Anders K.
Zhang Bo
Conexant Systems Inc.
Foley & Lardner
Nguyen Linh
Wells Kenneth B.
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