Pulse or digital communications – Miscellaneous
Reexamination Certificate
1999-02-02
2002-04-30
Corrielus, Jean (Department: 2731)
Pulse or digital communications
Miscellaneous
C713S400000, C713S600000
Reexamination Certificate
active
06381293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to data communication, and more particularly, to an apparatus for serial data communication among a plurality of integrated circuit (“IC”) chips which allows a reduced number of signal lines to be interconnected among the IC chips.
2. Description of the Related Art
In a chip set that includes several IC chips, a number of signal lines are often interconnected among the IC chips for data transmission among the same. The provision of a large number of signal lines in a chip set has several drawbacks. First, the size of the package increases in proportion to the number of signal lines. Second, the complexity of assembly of the chip set increases as the number of signal lines increases. Third, manufacturing cost is increased due to an increase in the chip area required to accommodate the large number of signal lines.
It is a customary practice to arrange the signal lines in parallel between two separate IC chips in order to attain a high data transmission rate. However, in order to minimumize the number of signal lines among a large number of IC chips, there are two conventional methods that can be used. The first method includes the use of multiplexers with time-share sampling, and the second method includes the use of serial transmission techniques. Examples of systems using these two methods are illustrated in FIG.
1
and FIG.
2
.
FIG. 1
illustrates an exemplary system using the method of multiplexing with time-share sampling, on a chip set that includes a first IC chip
10
and a second IC chip
11
. The first IC chip
10
includes a control unit
13
, a demultiplexer
14
, and four identical, independent data receiving units
120
,
121
,
122
,
123
. The second IC chip
11
includes a multiplexer
16
and four identical data transmitting units
150
,
151
,
152
,
153
associated respectively with the data receiving units
120
,
121
,
122
,
123
in the first IC chip
10
.
In the first IC chip
10
, the data receiving units
120
,
121
,
122
,
123
are wire connected to the demultiplexer
14
by the buses
17
a,
17
b,
17
c,
and
17
d,
respectively. In the second IC chip
11
, the data transmitting units
150
,
151
,
152
,
153
are wire connected to the multiplexer
16
by means of the buses
17
f,
17
g,
17
h,
and
17
i,
respectively. The demultiplexer
14
is wire connected to the multiplexer
16
by the bus
17
e.
Moreover. the demultiplexer
14
in the first IC chip
10
is wire connected to the control unit
13
, which is also in the first IC chip
10
, by the internal bus
18
, while the multiplexer
16
in the second IC chip
11
is wire connected to the control unit
13
by the external bus
19
. Since there are four source devices (i.e., the data transmitting units
150
,
151
,
152
,
153
) that are to be multiplexed by the multiplexer
16
for data transmission, and since there are four destination devices (i.e., the data receiving units
120
,
121
,
122
,
123
) that are to be selected by the demultiplexer
14
for reception of data from the source devices, therefore, the buses
18
,
19
each consist of two signal lines from the control unit
13
, serving to transmit a set of two control bits respectively to the multiplexer
16
and to the demultiplexer
14
for selecting a respective one of the four source devices. When a certain pair of data transmitting units and data receiving units is selected to use the common bus
17
e
for data transmission, for example, the second data transmitting unit
151
and the associated data receiving unit
121
, the control unit
13
generates two control bits which are sent respectively over the bus
18
and the bus
19
to the demultiplexer
14
and the multiplexer
16
. In response, in the first IC chip
10
the demultiplexer
14
connects the bus
17
b
to the receive end of the common bus
17
e
and, in the second IC chip
11
the multiplexer
16
connects the bus
17
g
to the transmit end of the common bus
17
e.
There are, however, two drawbacks to the system configuration of FIG.
1
. First, the clock rate of the control bits from the control unit
13
should be much faster than the data transmission rate in order to allow fast switching between the four multiplexed devices. Second, power consumption in the chip set is very high.
FIG. 2
illustrates an exemplary system using a serial transmission method on a chip set that includes a first IC chip
20
and a second IC chip
21
. A set of at least four signal lines
22
,
23
,
24
,
25
is used for data transmission between the first IC chip
20
and the second IC chip
21
. The signal line
22
allows the first IC chip
20
to transmit a Chip Select signal to the second IC chip
21
; the signal line
23
allows the first IC chip
20
to transmit a Serial Clock signal to the second IC chip
21
. The signal line
24
allows the second IC chip
21
to transmit serial binary data to the first IC chip
20
; the signal line
25
allows the first IC chip
20
to transmit serial binary data to the second IC chip
21
.
There are, however., two drawbacks to the system configuration of FIG.
2
. First, the number of signal lines between the two IC chips
20
,
21
is not minimumized since the data transmission between the two IC chips
20
,
21
is carried out over two separate lines (i.e., the signal lines
24
,
25
) rather than one. Second, data communication between the two IC chips
20
,
21
is under the control of a module in the first IC chip
20
, and the second IC chip
21
is unable to issue any requests for data transmission. Therefore, the system configuration of
FIG. 2
is not suitable for data communication among a large number of IC chips.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an apparatus for serial data communication using a reduced number of signal lines among a plurality of IC chips.
In accordance with the foregoing and other objects of the invention, a new and improved apparatus for serial data communication among a plurality of IC chips is provided. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to the master. In response to conditions internal to the master chip, or in response to a request from at least one slave chip, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer. The data communication between the IC chips requires only a reduced number of signal lines, which allows the number of pins required for connection of the two IC chips, as well as manufacturing costs, to be significantly reduced.
Thus, the apparatus according to the invention includes means for generating a transfer request signal and means for generating a transfer control signal and a synchronization clock signal in response to the transfer request signal, wherein the synchronization clock signal has a plurality of cycle periods. The apparatus also includes means for counting the cycle periods of the synchronization clock signal to produce a cycle count. A data transmitting means is provided for transmitting data in response to the transfer control signal under control of the cycle count. A data receiving means receives the data transmitted by the data transmitting means in response to the transfer control signal also under the control of the cycle count.
According to a further aspect of the invention, the means for generating a transfer request signal includes a first transfer request signal generating means located on the first IC chip and a second transfer request signal generating means located on the second IC chip. The means for generating a transfer control signal and a synchronization clock signal i
Huang Cheng-Wang
Lee David
Corrielus Jean
United Microelectronics Corp.
LandOfFree
Apparatus and method for serial data communication between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for serial data communication between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for serial data communication between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2879586