Apparatus and method for sensitive circuit protection with set-s

Cryptography – Particular algorithmic function encoding – Nbs/des algorithm

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380 3, 371 223, H04L 900

Patent

active

053575725

ABSTRACT:
A set/scan test capability is provided for a circuit that includes sensitive subcircuits, but that can be latched out to prevent reverse engineering the sensitive elements. A mechanism to inhibit set/scan test access to at least some of the sensitive subcircuits is selectively actuated by a control circuit to override a normal set/scan test and inhibit set/scan access to the sensitive subcircuits. Various implementations are possible, such as fusible-link PROMs for irreversibly inhibiting set/scan access to the sensitive subcircuits after an initial non-inhibited test period, the use of encryption codes to enable repeated set/scan access to the sensitive subcircuits, and an erasable/reprogrammable mechanism for inhibiting set/scan access to programmed sets of subcircuits.

REFERENCES:
patent: 4139864 (1979-02-01), Schulman
patent: 4267578 (1981-05-01), Vetter
patent: 4603381 (1986-07-01), Guttag
patent: 4833676 (1989-05-01), Koo
patent: 5109190 (1992-04-01), Sakashita et al.

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