Semiconductor device manufacturing: process – Including control responsive to sensed condition
Reexamination Certificate
2002-04-17
2003-02-18
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
C700S121000
Reexamination Certificate
active
06521466
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for semiconductor wafer yield enhancement, and more particularly to a semiconductor wafer test yield enhancement that integrates a defect detection and characterization system, and a defect eradication system.
BACKGROUND OF THE INVENTION
Surface cleaning of a semiconductor wafer has a significant bearing on device test yields. As the semiconductor industry pushes for smaller integrated circuit (IC) dimensions, e.g., 0.35 micron, 0.25 micron and 0.1 micron, the defect density level and size of the smallest particle capable of causing a failure in an IC decrease, as well. For example, for IC devices of 0.35 microns or less particles of the order of one third of the device size, i.e., 0.12 micron or less can cause the circuit to malfunction. Moore's Law projects that by 2005 IC devices will have over 700 million transistors per chip (FIG.
1
). The Semiconductor Industry Association (SIA) Roadmap projects that the 0.115 micron/300 millimeter wafer technology generation in 2005 will require a very low defect level of only 1260 defects per millimeter square for robust test yields.
Table 1 illustrates the effect of defect density level on test yield for several 0.18 micron products. For a 1 Gigabit dynamic RAM (DRAM) memory a decrease in defect density from 0.10 Defects/cm
2
to 0.01 Defects/cm
2
increases the device process yield from 12% to 81%. Similar yield increases are observed in a 1000 MIP Microprocessor and a System on a Chip (SOC) device. The results of Table 1 are included in an internal report presented to Applied Materials by Dr. Wayne Ellis and Paul Castrucci, entitled “AMAT Scenario 2003-IC Yield Analysis” October 1998, incorporated herein by reference.
The IC industry needs technology tools that will eradicate defects in order to achieve the very low defect levels required to produce products with very fine feature sizes while maintaing commercially viable wafer processes with high test yields.
TABLE 1
Defect Density
Product
(Defects/cm
2
)
Test Yield (%)
1 Gigabit DRAM
0.01
81
1 Gigabit DRAM
0.03
53
1 Gigabit DRAM
0.1
12
Microprocessor (1000 MIP)
0.01
70
Microprocessor (1000 MIP)
0.03
28
Microprocessor (1000 MIP)
0.1
12
System on a Chip (SOC)
0.01
64
System on a Chip (SOC)
0.03
25
System on a Chip (SOC)
0.1
12
Surface defects of an IC include surface structural disorders and discrete pieces of matter that range in size from submicron dimension to granules visible to observation with the eye. Surface structural disorders include microscratches, metal etching stringers, missing contacts, and bridging due to tungsten residue during chemical mechanical polishing (CMP). Discrete pieces of matter may be fine dust, dirt particles, foreign molecules including carbon, hydrogen, and/or oxygen. Particulate contaminants (“particulates”) frequently adhere to a surface by weak covalent bonds, electrostatic forces, van der Waals forces, hydrogen bonding, coulombic forces, or dipole-dipole interactions, making removal of the particulates difficult. Particulates frequently encountered in practice include polysilicon slivers, photoresist particles, metal oxide particles, and slurry residue. It is known that not all particulates are equally undesirable. For example, particulates that adhere at some non-sensitive portions of the IC circuitry may have no effect on operation or performance, and need not necessarily be removed (“don't cares”). On the other hand, particulates that adhere to active areas or critical locations (“killer defects”) can cause failure of the IC circuitry and must be removed for proper operation.
Semiconductor surface cleaning technology involves breaking the above mentioned adhesion bonds and removal of the contaminants. The known methods of semiconductor surface cleaning include chemical wet-processes, e.g. RCA and Piranha etch, chemical dry-processes, mechanical processes, thermal, ultrasonic, optical techniques and combinations thereof. The chemical wet-processes require large amounts of chemical solutions and water. These chemical solutions are expensive, frequently introduce new contaminants, and their disposal causes an environmental problem. Thermal processes require in some cases melting of the top surface and removal via ultra high vacuum pressure. The melting of the top layer may disturb the integrity of the previously deposited layers and the high vacuum equipment are both expensive and time consuming to operate. Thermal annealing does not require melting of the top surface. However, it requires longer exposure to temperatures below the melting point, which may cause undesired diffusion of particles and changes of the crystalline structure.
Gas-phase chemical dry-cleaning processes have been used for years to clean semiconductor surfaces. Among the various chemical dry-cleaning processes, the supercritical fluid cleaning process offers many advantages.
At temperatures above 31° C. and pressure of 1072 psi, the liquid and gaseous phases of CO
2
combine to form supercritical CO
2
(SCCO2). Supercritical fluid possesses liquid-like solution and gas-like diffusion properties. SCCO2 has low viscosity and low dielectric constant. The low viscosity of SCCO2 enables rapid penetration into crevices, pores, trenches and vias with complete removal of both organic and inorganic contaminants. Organic contaminants that can be removed with SCCO2 include oils, grease, organic films, photoresist, plasticizers, monomers, lubricants, adhesives, fluorinated oils and surfactants. Inorganic contaminants that can be removed with SCCO2 include metals, metal complexing agents, inorganic particulates. Contaminants solvate within the SCCO2 and are evacuated into a low pressure chamber, where they become insoluble and are precipitated from the liquid CO
2
. The supercritical fluid technology cleaning tool SCF-CT apparatus has a small footprint of about 75 square feet and sells for about $500K to $1M. Conventional water clean benches cost over $2M. The process of cleaning semiconductor surfaces using SCCO2 is described in a technical paper entitled “Precision Cleaning of Semiconductor Surfaces Using Carbon Dioxide Based Fluids” by J. B. Rubin, L. D. Sivils, and A. A. Busnaina published in Proceedings SEMICON WEST 99, Symposium On Contamination Free Manufacturing for Semiconductor Processing, San Francisco, Calif. Jul. 12-14, 1999, the entire content of which is expressly incorporate herein by reference.
While cleaning of semiconductor surfaces with SCCO2 has proven to be effective for removing particles, improved cleaning results are required before this process can become commercially successful. In particular, an intelligent cleaning system that incorporates defect diagnostics, optimal cleaning based on SCF-CT unique parameters, and defect eradication is desirable.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention features a semiconductor wafer processing apparatus including equipment for identifying and characterizing surface defects on each wafer at at least one processing station and for creating a record of the surface defect data for each wafer and equipment for performing supercritical fluid cleaning of the wafers. The equipment for supercritical cleaning is adapted to receive the surface defect data from the created record and apply a supercritical fluid cleaning recipe based on the surface defect data. The apparatus further includes equipment for transferring a plurality of semiconductor wafers among a plurality of processing stations under computer control and equipment for transferring of cleaned wafers to an output station.
Implementations of this aspect of the invention may include one or more of the following features. The surface defect identification and characterization data may include position coordinates, type, density and size of surface defects on each wafer. The equipment for identifying and characterizing surface defects on each wafer may be an advanced patterned wafer inspection system with an automatic defect classification program. The advanced
AKC Patents
Collins Aliki K.
Cuneo Kamand
Pert Evan
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