Apparatus and method for self-timed marking of variable length i

Details Apparatus and method for self-timed marking of variable length i Apparatus and method for self-timed marking of variable length i

1997-12-23

1999-09-07

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

712212, 712213, 712245, 712246, G06F 930

Patent

active

059480963

ABSTRACT:
A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

REFERENCES:
patent: 4680701 (1987-07-01), Cochran
patent: 5347639 (1994-09-01), Rechtschaffen
patent: 5535347 (1996-07-01), Grochowski
patent: 5553276 (1996-09-01), Dean
patent: 5758116 (1998-05-01), Lee
patent: 5870599 (1999-02-01), Hinton

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