Multiplex communications – Wide area network – Packet switching
Patent
1994-11-10
1996-02-20
Kizou, Hassan
Multiplex communications
Wide area network
Packet switching
370 941, 371 202, H04B 1702, H04J 314
Patent
active
054935628
ABSTRACT:
A circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure.
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