Electrical computers and digital processing systems: multicomput – Network computer configuring – Initializing
Patent
1997-10-30
1999-08-17
Harrell, Robert B.
Electrical computers and digital processing systems: multicomput
Network computer configuring
Initializing
G06F 1312
Patent
active
059387289
ABSTRACT:
A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables the network interface device to initialize upon power up and start to monitor network media for wakeup traffic indicating the host computer in the workstation should be activated.
REFERENCES:
patent: 5708820 (1998-01-01), Park et al.
patent: 5809223 (1998-09-01), Lee et al.
Dwork Jeffrey Roy
Roy Rajat
Williams Robert Alan
Yu Ching
Advanced Micro Devices , Inc.
Harrell Robert B.
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