Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2008-05-27
2008-05-27
Kindred, Alford (Department: 2181)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S218000
Reexamination Certificate
active
10144589
ABSTRACT:
A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix precludes write back of the result, where the result is that which is produced by executing an operation prescribed by said extended instruction, and wherein the result would otherwise be written back into a destination register. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the operation to generate the result, and precludes write back of the result.
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Henry G. Glenn
Hooker Rodney E.
Parks Terry
Huffman James W.
Huffman Richard K.
iP-First, LLC
Kindred Alford
Moll Jesse R
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