Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-12-15
2003-03-11
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06532486
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to processors and, more particularly, to an apparatus and method for saturating data in a register on a processor.
BACKGROUND OF THE INVENTION
Digital signal processors (DSPs) are widely used in many devices that typically interface with some type of control device. Frequently, the word length of the data provided to the DSP by the control device is shorter than the word length of the DSP registers. In many control algorithms, such as state estimators, PID, and kalman filters, intermediate and final results may need to be saturated. Saturation sets the register, such as an accumulator, to a maximum or minimum value. The saturation value of the control algorithm in the register must be compatible with the control device, i.e., the saturation value must be the same length as the control device word length. Processors and corresponding devices may have instructions for saturation operations. Generally, these operations only saturate when the full value of the register is exceeded. For example, a 32-bit register will be saturated when a value exceeds the limits of the 32-bit register range.
In some devices instructions are provided that will saturate the register at any bit position. These instructions may include multiple steps and cycles. For example, the following instructions may be executed to saturate a 16-bit value in a 32-bit register. First, saturation mode is enabled on the processor. Second, a saturation value, which is stored in a memory location, is added to bits
16
-
31
of the register. Third, the saturation value is subtracted from these bits of the register. Fourth, the saturation value is again subtracted from these bits of the register. Finally, the saturation value is added to these bits of the register. This method requires five instructions and five cycles to implement. A 32-bit value may require up to nine instructions and nine cycles to implement. The above method also requires data memory read and write operations and, thus, increased power consumption. Further, it also requires memory locations to store the saturation values for each particular saturation range. Thus, these techniques for saturating at any bit position require additional silicon or additional software instructions to implement.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a method for saturating contents in a register at any bit position with a reduced number of instructions, and without the need for memory space. In accordance with the present invention, an apparatus and method for saturating contents in a register is provided that substantially eliminates and reduces the disadvantages and problems associated with conventional register operations.
A method for saturating data in a register on a processor in accordance with the present invention comprises five steps. The first step comprises shifting the data contents in the register by a saturation value and setting at least one bit equal to a sign bit on the register. The second step comprises storing the shifted contents in a temporary register, wherein the temporary register has compare bits. The third step comprises setting high bits and low bits of the register to a positive value when the compare bits of the temporary register are not equal to the sign bit, and the sign bit indicates a positive data word in the register. The fourth step comprises setting the high bits and the low bits of the register to a negative value when the compare bits of the temporary register are not equal to the sign bit, and the sign bit indicates a negative data word in the register. The fifth step comprises shifting the set data contents in the register by the saturation value and setting at least one bit equal to a least significant bit on the register.
In another embodiment, a method for saturating data in a register on a processor in accordance with the present invention comprises five steps. The first step comprises right shifting the data contents in the register by a saturation value, and setting at least one bit equal to a sign bit, wherein the sign bit is on the register. The second step comprises storing the shifted data contents in a temporary register. The third step comprises comparing the sign bit to the shifted contents in the temporary register. The fourth step comprises setting the bits in the register equal to 1 when the shifted contents in the temporary register are not equal to the sign bit, and when the sign bit is equal to 0, and then left shifting the set data contents in the register by the saturation value, and setting at least one bit equal to 1. The fifth step comprises setting the bits in the register equal to 0 when the shifted contents in the temporary register are not equal to the sign bit, and when the sign bit is equal to 1, and then left shifting the set data contents in the register by the saturation value, and setting at least one bit equal to 0.
In another embodiment, an apparatus for saturating data in a register on a processor in accordance with the present invention is disclosed. The register has a sign bit, a least significant bit, high bits and low bits. The apparatus also has a shifting device, wherein the data contents in the register are shifted by a saturation value. The apparatus also has a temporary register having compare bits, wherein the shifted contents of the register are stored. The apparatus also has a device for setting high bits and low bits of the register to a positive value when the compare bits of the temporary register are not equal to the sign bit, and the sign bit indicates a positive data word in the register. The device also sets the high bits and the low bits of the register to a negative value when the compare bits of the temporary register are not equal to the sign bit, and the sign bit indicates a negative data word in the register.
A technical advantage of the present invention is that a method for saturating data in a register on a processor is provided. Another technical advantage is that overflow problems are resolved on the register. Another technical advantage is that compatibility with devices requiring a variety of data sizes may be achieved. Another technical advantage is that saturation operations may be performed in a reduced number of cycles. Another technical advantage is that saturation operations may be executed without requiring additional memory or software. Another technical advantage is that the register may be saturated at any user specified bit position with a reduced number of instructions and cycles. Another technical advantage is that any register size may be saturated in accordance with the present invention. Another technical advantage is that data memory read and write operations are avoided. Another technical advantage is that power consumption requirements are reduced.
REFERENCES:
patent: 5915109 (1999-06-01), Nakakimura et al.
patent: 5917740 (1999-06-01), Volkonsky
patent: 5936870 (1999-08-01), Im
patent: 6209017 (2001-03-01), Lim et al.
patent: 6237084 (2001-05-01), Morikawa et al.
Brady W. James
Malzahn David H.
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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