Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Patent
1997-10-03
1999-05-11
Hoff, Marc S.
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
3647241, H03M7/00
Patent
active
059032324
ABSTRACT:
A rational decimation circuit (200) has an integration filter (210) and an FIR-filter (220). The integration filter (210) has N serially arranged integrator blocks (230-n) and an interpolator block (250). The FIR-filter (220) has K filter channels (260-k) and a commutator (290) which are controlled by a control block (300). Each channel (260-k) has a multiplier unit (270-k) and an accumulator unit (280-k).
The integration filter (210) has a transfer function with N-fold poles and the FIR-filter (220) has a transfer function with zeros which cancel the poles. FIR-coefficients h.sub.k (T.sub.V) in the FIR-filter (220) are related to the F.sub.V /F.sub.X ratio of the interpolator block (250) and to the number N of integrator blocks (230-n). A method is also described.
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Koifman Vladimir
Sand Eliezer
Zarubinsky Michael
Hoff Marc S.
Motorola Inc.
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