Patent
1996-07-24
1999-05-11
Lall, Parshotam S.
395380, 395391, 395392, 39580023, 39580026, G06F9/00;9/40
Patent
active
059037407
ABSTRACT:
A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement. The present invention advantageously increases the size of the retire window. Accordingly, if two or more retired instructions output to the same register, an additional instruction from the retire window can be retired. The additional instruction utilizes the write port not used by the older of the instructions that output to the same register. Thereby, the reorder buffer is emptied at a faster rate and causes less instruction dispatch stalls.
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Barot Bharat
Kivlin B. Noel
Lall Parshotam S.
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