Apparatus and method for resolving dependencies among a pluralit

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364DIG2, 3649336, 3649472, 3649462, G06F 906

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active

053455690

ABSTRACT:
An apparatus and method for resolving data dependencies among a plurality of instructions within a storage device, such as a reorder buffer in a superscalar computing apparatus employing pipeline instruction processing. The storage device has a read pointer, indicating a most recently-stored instruction and has a write pointer, indicating a first-stored instruction of the plurality of instructions within the storage device.
A compare-hit circuit generates a compare-hit signal upon each concurrence of the respective source indicator in a next-to-be-dispatched instruction with the destination indicator of an earlier-stored instruction within the storage device; a first enable circuit generates a first enable signal for a first packet of instructions defined by the read pointer and the write pointer; a first comparing circuit generates a hit-enable signal for each concurrence of the compare-hit signal and the first enable signal; a second enable circuit generates a second enable signal for a second packet of instructions defined by the read pointer and the hit-enable signal; and a second comparing circuit generates the output signal for each concurrence of the second enable signal and the hit-enable signal.

REFERENCES:
patent: 4714994 (1987-12-01), Oklobdzija et al.
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 5226126 (1993-07-01), McFarland et al.

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