Pulse or digital communications – Cable systems and components
Reexamination Certificate
1998-07-30
2001-05-29
Pham, Chi (Department: 2731)
Pulse or digital communications
Cable systems and components
C375S288000, C375S220000, C375S211000, C370S297000
Reexamination Certificate
active
06240139
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to data communications, and in particular, to a repeater circuit for repeating multiple signals which have been simultaneously transmitted on a single transmission path. The invention also encompasses a method for repeating multiple signals which have been simultaneously transmitted on a single transmission path.
BACKGROUND OF THE INVENTION
Many digital circuit applications require communications between separate circuits implemented on different integrated circuit chips. Digital signals are communicated from one chip to another through a suitable transmission line or path. As used herein, “digital signals” refers to signals which reside at one of two signal voltage levels, a “low” voltage level representing one data state and a “high” voltage level representing the opposite data state. For example, a “low” voltage level signal may represent a “0” while a “high” voltage level signal may represent a “1”. Often times a system may require that multiple signals be transmitted from one chip to another in the system. In these cases in which multiple signals must be communicated, the multiple signals may be communicated on different transmission lines or time division multiplexed on a single transmission line. In time division multiplexing, the multiple signals are simply transmitted at different times on the single transmission line.
Although time division multiplexing allows multiple signals to be transmitted over a single transmission line, it requires additional complex circuitry. In order to avoid the circuit complexity occasioned by time division multiplexing, system designs have often settled for using separate transmission lines in order to support simultaneous data communications in a single direction. However, multiple transmission lines also add complexity due to the added drivers, receivers, chip pins, and signal pads which the multiple transmission lines require. It is therefore also desirable to reduce the number of transmission lines between integrated circuit chips thereby reducing the corresponding connection, transmission, and reception circuitry.
U.S. patent application Ser. No. 08/387,518 is directed to a circuit for allowing simultaneous unidirectional data communications through a single transmission line. According the system disclosed in that application, two digital data signals are encoded into a single encoded signal which represents both original digital signals. The encoded signal is transmitted through a single transmission line to a second circuit which decodes the encoded signal back into the first and second digital data signals for use by the circuit on the receiving integrated circuit chip.
All transmission lines exhibit a parasitic resistance to the transmitted signals. For relatively short transmission lines this parasitic resistance is negligible and does not affect the transmitted signals. However, as the length of the transmission line increases the parasitic resistance may increase to the point at which the transmitted signal degrades sufficiently to cause an error in reading the transmitted data. The simultaneous signal transmission arrangement disclosed in patent application Ser. No. 08/387,518 is particularly susceptible to errors caused by signal degradation due to parasitic resistance in transmission lines. Since the encoded signal described in this patent application resides at one of four voltage levels between a supply voltage and ground, relatively little signal degradation may result in an error when decoding the encoded signal back to the desired data signals.
SUMMARY OF THE INVENTION
It is an object of invention to provide a repeater circuit for repeating an encoded signal representing two distinct digital signals. Another object of invention is to provide a method for repeating such an encoded signal.
These objects are accomplished in a repeater circuit comprising a decoding arrangement and an encoder arrangement coupled between an input transmission path and an output transmission path. The decoding arrangement includes two decoders which both receive an input encoded signal representing a first data signal and a second data signal. A first decoder decodes the input encoded signal to produce the first data signal. A second decoder decodes the input encoded signal to produce the second data signal. The first and second data signals serve as inputs to the encoder arrangement which re-encodes these signals to produce an output encoded signal representing the first and second data signals. This output encoded signal is then transmitted via an output transmission path on to the next repeater circuit or a destination circuit which requires the first and second data signals. The repeater circuit according to the invention serves to restore the value of the encoded signal which may have degraded by the parasitic resistance associated with the input transmission path.
The first and second data signals each comprise digital signals having one of two signal voltage levels, a “low” voltage level or a “high” voltage level. The input and output encoded signals each comprise a signal at any one of four voltage levels. Each of the four encoder voltage levels represent a particular combination of the data signals. One encoder voltage level represents “low” first and second data signals, while another encoder voltage level represents “high” first and second data signals. Yet another encoder voltage level represents a “low” first data signal and a “high” second data signal, and a final encoder voltage level represents a “high” first data signal and a “low” second data signal.
The first decoder of the repeater circuit comprises a first differential receiver which compares the input encoded signal to a reference voltage and provides the first data signal at the differential receiver output. A second differential receiver and a non-inverting buffer make up the second decoder. The buffer receives the first data signal at the buffer input and produces a buffer output. The second receiver compares the input encoded signal to the buffer output and produces the second data signal from this comparison.
Once decoded into the first and second data signals, the two data signals are applied as inputs to the encoder portion of the repeater circuit. The encoder comprises a voltage divider arrangement having two impedance paths coupled to the output transmission path through an output node. A first impedance path includes a first driver and a first resistor. A second impedance path includes a second driver and a second resistor. The impedances of the first impedance path and the second impedance path are preselected so that the encoder produces a different one of the four encoder voltage levels at the output node in response to each different combination of first and second data signals.
In one form, the repeater circuit according to the invention is adapted to repeat an input signal representing only a single one of the first or second data signals. In this form of the invention each driver in the encoder arrangement is connected to receive a disable signal. When applied to one of the encoder drivers, the disable signal places the particular driver in a disabled or tri-state condition. The disable signal to one of the drivers also causes a compensating impedance to be applied to the remaining impedance path. The compensating impedance causes the total impedance of the remaining impedance path to match the impedance of the output transmission path.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.
REFERENCES:
patent: 4498166 (1985-02-01), Esposito
patent: 5469430 (1995-11-01), Guerin et al.
patent: 5799040 (1998-08-01), Lau
patent: 5856980 (1999-01-01), Doyle
patent: 5929896 (1999-07-01), Goodman et al.
Cao Tai Ahn
Dutta Satyajit
Luk Donna W.
Carwell Robert M.
Culbertson Russell D.
Emmanuel Bayard
International Business Machines - Corporation
Pham Chi
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