Cleaning and liquid contact with solids – Processes – For metallic – siliceous – or calcareous basework – including...
Reexamination Certificate
2002-01-07
2004-01-27
Carrillo, Sharidan (Department: 1746)
Cleaning and liquid contact with solids
Processes
For metallic, siliceous, or calcareous basework, including...
C134S006000, C134S018000, C134S024000, C134S026000, C134S028000, C134S029000, C134S032000, C134S033000, C134S034000, C134S041000, C134S042000, C134S147000, C134S148000, C134S153000, C134S902000
Reexamination Certificate
active
06682605
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to an apparatus and a method for removing coating layers from alignment marks on a wafer and more particularly, relates to an apparatus and a method for removing coating layers from the alignment marks by mounting two additional solvent dispensing nozzles in an edge bevel removal (EBR) chamber for spraying a solvent on the coating layers while the wafer is held in a stationary position.
BACKGROUND OF THE INVENTION
Deposition and patterning are two of the basic steps performed in semiconductor processing. Patterning is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of deposition. For example, as shown in
FIG. 1A
, a layer
104
has been deposited on a substrate
102
. After the photolithography process is performed, as shown in
FIG. 1B
, some parts of the layer
104
have been selectively removed, such that gaps
106
a
and
106
b
are present within the layer
104
. A photomask, or pattern, is used (not shown in
FIG. 1B
) so that only the material from the gaps
106
a
and
106
b
are removed, and not the other portions of the layer
104
. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes. This is shown in
FIG. 2
, where the semiconductor wafer
202
has alignment marks, such as the alignment square
204
, thereon. When the photomask
206
is positioned over the wafer
202
, its own alignment marks, such as the alignment square
208
, is aligned with the alignment marks of the wafer
202
. For example, the alignment square
208
of the photomask
206
is aligned so that the alignment square
204
of the wafer
202
is centered therein.
Alignment is especially critical where more a number of metal or other layers have already been deposited on the wafer. Subsequent deposition of silicon dioxide or other layers in such instances usually requires that the alignment marks on the wafer be exposed for proper overlay of the silicon dioxide or other layers. While a mask may prevent the layers themselves from obfuscating the alignment marks, the photoresist used to pattern or perform other processing of these layers cannot be masked, and covers or at least blurs the alignment marks. Without clear exposure of the alignment marks, however, overlay misalignment can result. Overlay misalignment is also referred to as overlay registration error. Misalignment is a serious problem, and can result in significant semiconductor wafer scrap. Wafer scrap can sometimes be reused, but often is discarded, resulting in added costs incurred by the semiconductor foundry.
In the recent development of semiconductor fabrication technologies, copper has been widely used in devices of 0.18 &mgr;m or smaller as vias or interconnects. A widely used technique for depositing copper on a semiconductor wafer is the electrochemical plating method. However, when copper is deposited onto a wafer surface by the electrochemical plating method, alignment marks on the wafer are also covered with a layer of copper and a layer of TaN which is used as a diffusion barrier for copper. If the Cu/TaN layers over the alignment marks are not completely removed in a later process, alignment failure occurs in a future photolithographic step.
Presently, a process of edge bevel removal (EBR) is used to remove a circular band of Cu/TaN at the wafer edge. This is shown in FIG.
3
. Wafer
302
, which has alignment marks
304
and
306
formed on an active surface
308
, is cleaned by using a cleaning solution such that a circular band
310
of Cu/TaN at the wafer edge is removed. Although the Cu/TaN layers over the alignment marks
304
,
306
is removed, the cleaning procedure inevitably results in die loss along the circular band
310
. For instance, as shown in
FIG. 3
, the IC dies
312
~
330
are all lost due to the EBR process.
A typical electrochemical plating (ECP) apparatus
400
which includes an edge bevel removal (EBR) chamber
402
is shown in FIG.
4
. The EBR chamber is arranged in a stacked bevel clean and spin rinse/dry chambers for convenient wafer transfer and space saving. The electrochemical plating apparatus
400
further includes two loadlock chambers
404
,
406
for loading/unloading unprocessed/processed wafers into and out of the apparatus
400
. Wafer transfer stations
408
and
410
are used to transfer wafers between the loadlock chambers
404
,
406
, the EBR chambers
402
and the anneal chambers
412
and
414
. Within the apparatus
400
, is a dual-blade robot
416
used to transfer wafers between the process stations
418
,
420
each having a dual cell arrangement for conducting the electro-chemical plating operation. As previously shown in
FIG. 3
, while the EBR chamber
402
is able to remove coating layers from the top of alignment marks
304
,
306
, the excessive number of IC dies that are lost due to the edge bevel removal process cannot be tolerated if a high fabrication yield is desired.
It is therefore an object of the present invention to provide an apparatus for removing coating layers from alignment marks that does not have the drawbacks or the shortcomings of the conventional apparatus.
It is another object of the present invention to provide an apparatus for removing coating layers from alignment marks on a wafer in an edge bevel removal chamber of a plating apparatus.
It is a further object of the present invention to provide an apparatus for removing coating layers from the top of alignment marks by installing at least two solvent spray nozzles in an edge bevel removal chamber for removing the coating layers while the wafer is held in a stationary position.
It is another further object of the present invention to provide an apparatus for removing coating layers from the top of alignment marks on a wafer by first spraying a solvent on the alignment marks while the wafer is stationary and then spraying solvent on the edge bevel while the wafer is rotated.
It is still another object of the present invention to provide an apparatus for removing coating layers from the top of alignment marks by spraying a H
2
SO
4
-containing solvent on the coating layers while the wafer is held in a stationary position.
It is yet another object of the present invention to provide a method for removing coating layers from the top of alignment marks on a wafer in a wafer edge cleaning chamber of an electrochemical plating apparatus.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and a method for removing coating layers from the top of alignment marks in a wafer edge bevel removal chamber are disclosed.
In a preferred embodiment, a wafer edge bevel removal chamber for cleaning wafer edge alignment marks is provided which includes a cleaning chamber that has a cavity therein and a lid member suspended in the cavity; a wafer chuck rotatably mounted in the lid member for holding a wafer with an active surface of the wafer and at least two alignment marks on the active surface in a faced-down position; and at least two solvent dispensing arms mounted in an outer peripheral area of the lid member adjacent to the chuck for dispensing a flow of solvent upwardly toward the active surface of the wafer when the wafer is held in a stationary position, each of the at least two solvent dispensing arms are positioned corresponding to a position of one of the alignment marks.
In the wafer edge bevel removal chamber for cleaning wafer edge
Chen Chun-Chang
Cheng Aaron
Lin Yu-Ku
Wang Ting-Chun
Wang Yi-Lang
Carrillo Sharidan
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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